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authorKenneth Graunke <[email protected]>2019-05-03 14:20:00 -0700
committerKenneth Graunke <[email protected]>2019-05-14 13:16:24 -0700
commitd86260719ed800e16270371faad6ba29b42d3c84 (patch)
tree78f1a43fabd5242f2e9bda0fc280c7e89d2aa104
parent381c2aded223abce3635b530334f0f0ae8b8397c (diff)
intel/compiler: Refactor TCS invocation ID setup into a helper
When we add 8_PATCH mode, this will get a bit more complex, so we may as well start by putting it in a helper function. Reviewed-by: Jason Ekstrand <[email protected]>
-rw-r--r--src/intel/compiler/brw_fs.cpp35
-rw-r--r--src/intel/compiler/brw_fs.h2
2 files changed, 23 insertions, 14 deletions
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index c942a35a434..370cd184b89 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -7392,20 +7392,16 @@ fs_visitor::run_vs()
return !failed;
}
-bool
-fs_visitor::run_tcs_single_patch()
+void
+fs_visitor::set_tcs_invocation_id()
{
- assert(stage == MESA_SHADER_TESS_CTRL);
-
struct brw_tcs_prog_data *tcs_prog_data = brw_tcs_prog_data(prog_data);
- /* r1-r4 contain the ICP handles. */
- payload.num_regs = 5;
+ const unsigned invocation_id_mask =
+ devinfo->gen >= 11 ? INTEL_MASK(22, 16) : INTEL_MASK(23, 17);
+ const unsigned invocation_id_shift =
+ devinfo->gen >= 11 ? 16 : 17;
- if (shader_time_index >= 0)
- emit_shader_time_begin();
-
- /* Initialize gl_InvocationID */
fs_reg channels_uw = bld.vgrf(BRW_REGISTER_TYPE_UW);
fs_reg channels_ud = bld.vgrf(BRW_REGISTER_TYPE_UD);
bld.MOV(channels_uw, fs_reg(brw_imm_uv(0x76543210)));
@@ -7414,10 +7410,6 @@ fs_visitor::run_tcs_single_patch()
if (tcs_prog_data->instances == 1) {
invocation_id = channels_ud;
} else {
- const unsigned invocation_id_mask = devinfo->gen >= 11 ?
- INTEL_MASK(22, 16) : INTEL_MASK(23, 17);
- const unsigned invocation_id_shift = devinfo->gen >= 11 ? 16 : 17;
-
invocation_id = bld.vgrf(BRW_REGISTER_TYPE_UD);
/* Get instance number from g0.2 bits 23:17, and multiply it by 8. */
@@ -7429,6 +7421,21 @@ fs_visitor::run_tcs_single_patch()
bld.ADD(invocation_id, instance_times_8, channels_ud);
}
+}
+
+bool
+fs_visitor::run_tcs_single_patch()
+{
+ assert(stage == MESA_SHADER_TESS_CTRL);
+
+ /* r1-r4 contain the ICP handles. */
+ payload.num_regs = 5;
+
+ if (shader_time_index >= 0)
+ emit_shader_time_begin();
+
+ /* Initialize gl_InvocationID */
+ set_tcs_invocation_id();
/* Fix the disptach mask */
if (nir->info.tess.tcs_vertices_out % 8) {
diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h
index 098725b80d1..6ff90e3ce49 100644
--- a/src/intel/compiler/brw_fs.h
+++ b/src/intel/compiler/brw_fs.h
@@ -194,6 +194,8 @@ public:
bool opt_cmod_propagation();
bool opt_zero_samples();
+ void set_tcs_invocation_id();
+
void emit_nir_code();
void nir_setup_outputs();
void nir_setup_uniforms();