i965: Use ISL for emitting depth/stencil/hiz state on gen6+

We leave gen4-5 alone because the ISL code hasn't really been well-
tested on gen4-5 or with combined depth-stencil because we don't use
BLORP for depth operations on gen4-5.  Also, the gen4-5 code has to deal
with intratile offsets for LOD hacks and ISL doesn't handle those yet.
We could make ISL handle gen4-5 capable or we could just not bother.

Among other things, this should make future platform enabling easier
because it means we don't have to update multiple (or hand-rolled!)
depth stencil emit paths.

Reviewed-by: Kenneth Graunke <[email protected]>

9 files changed, 129 insertions, 671 deletions

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources b/src/mesa/drivers/dri/i965/Makefile.sources
index 5e53d874d88..db6591ab90a 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -68,14 +68,12 @@ i965_FILES = \
 	gen4_blorp_exec.h \
 	gen6_clip_state.c \
 	gen6_constant_state.c \
-	gen6_depth_state.c \
 	gen6_multisample_state.c \
 	gen6_queryobj.c \
 	gen6_sampler_state.c \
 	gen6_sol.c \
 	gen6_urb.c \
 	gen7_l3_state.c \
-	gen7_misc_state.c \
 	gen7_sol_state.c \
 	gen7_urb.c \
 	gen8_depth_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index b954a2916d9..ec3fe3be40d 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -922,15 +922,6 @@ brwCreateContext(gl_api api,
    brw->gs.base.stage = MESA_SHADER_GEOMETRY;
    brw->wm.base.stage = MESA_SHADER_FRAGMENT;
    brw->cs.base.stage = MESA_SHADER_COMPUTE;
-   if (devinfo->gen >= 8) {
-      brw->vtbl.emit_depth_stencil_hiz = gen8_emit_depth_stencil_hiz;
-   } else if (devinfo->gen >= 7) {
-      brw->vtbl.emit_depth_stencil_hiz = gen7_emit_depth_stencil_hiz;
-   } else if (devinfo->gen >= 6) {
-      brw->vtbl.emit_depth_stencil_hiz = gen6_emit_depth_stencil_hiz;
-   } else {
-      brw->vtbl.emit_depth_stencil_hiz = brw_emit_depth_stencil_hiz;
-   }
 
    brw_init_driver_functions(brw, &functions);
 
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 23406816a9b..d8b0d94aaff 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -742,20 +742,6 @@ struct brw_context
    struct
    {
       /**
-       * Send the appropriate state packets to configure depth, stencil, and
-       * HiZ buffers (i965+ only)
-       */
-      void (*emit_depth_stencil_hiz)(struct brw_context *brw,
-                                     struct intel_mipmap_tree *depth_mt,
-                                     uint32_t depth_offset,
-                                     uint32_t depthbuffer_format,
-                                     uint32_t depth_surface_type,
-                                     struct intel_mipmap_tree *stencil_mt,
-                                     bool hiz, bool separate_stencil,
-                                     uint32_t width, uint32_t height,
-                                     uint32_t tile_x, uint32_t tile_y);
-
-      /**
        * Emit an MI_REPORT_PERF_COUNT command packet.
        *
        * This asks the GPU to write a report of the current OA counter values
@@ -1708,45 +1694,6 @@ brw_depth_writes_enabled(const struct brw_context *brw)
 void
 brw_emit_depthbuffer(struct brw_context *brw);
 
-void
-brw_emit_depth_stencil_hiz(struct brw_context *brw,
-                           struct intel_mipmap_tree *depth_mt,
-                           uint32_t depth_offset, uint32_t depthbuffer_format,
-                           uint32_t depth_surface_type,
-                           struct intel_mipmap_tree *stencil_mt,
-                           bool hiz, bool separate_stencil,
-                           uint32_t width, uint32_t height,
-                           uint32_t tile_x, uint32_t tile_y);
-
-void
-gen6_emit_depth_stencil_hiz(struct brw_context *brw,
-                            struct intel_mipmap_tree *depth_mt,
-                            uint32_t depth_offset, uint32_t depthbuffer_format,
-                            uint32_t depth_surface_type,
-                            struct intel_mipmap_tree *stencil_mt,
-                            bool hiz, bool separate_stencil,
-                            uint32_t width, uint32_t height,
-                            uint32_t tile_x, uint32_t tile_y);
-
-void
-gen7_emit_depth_stencil_hiz(struct brw_context *brw,
-                            struct intel_mipmap_tree *depth_mt,
-                            uint32_t depth_offset, uint32_t depthbuffer_format,
-                            uint32_t depth_surface_type,
-                            struct intel_mipmap_tree *stencil_mt,
-                            bool hiz, bool separate_stencil,
-                            uint32_t width, uint32_t height,
-                            uint32_t tile_x, uint32_t tile_y);
-void
-gen8_emit_depth_stencil_hiz(struct brw_context *brw,
-                            struct intel_mipmap_tree *depth_mt,
-                            uint32_t depth_offset, uint32_t depthbuffer_format,
-                            uint32_t depth_surface_type,
-                            struct intel_mipmap_tree *stencil_mt,
-                            bool hiz, bool separate_stencil,
-                            uint32_t width, uint32_t height,
-                            uint32_t tile_x, uint32_t tile_y);
-
 uint32_t get_hw_prim_for_gl_prim(int mode);
 
 void
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 0ab1f128011..e44baf25185 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -254,6 +254,16 @@ brw_workaround_depthstencil_alignment(struct brw_context *brw,
        rebase_depth_stencil(brw, stencil_irb, invalidate_stencil);
 }
 
+static void
+brw_emit_depth_stencil_hiz(struct brw_context *brw,
+                           struct intel_mipmap_tree *depth_mt,
+                           uint32_t depth_offset, uint32_t depthbuffer_format,
+                           uint32_t depth_surface_type,
+                           struct intel_mipmap_tree *stencil_mt,
+                           bool hiz, bool separate_stencil,
+                           uint32_t width, uint32_t height,
+                           uint32_t tile_x, uint32_t tile_y);
+
 void
 brw_emit_depthbuffer(struct brw_context *brw)
 {
@@ -337,28 +347,129 @@ brw_emit_depthbuffer(struct brw_context *brw)
    if (stencil_mt)
       brw_cache_flush_for_depth(brw, stencil_mt->bo);
 
-   brw->vtbl.emit_depth_stencil_hiz(brw, depth_mt, depth_offset,
-                                    depthbuffer_format, depth_surface_type,
-                                    stencil_mt, hiz, separate_stencil,
-                                    width, height, tile_x, tile_y);
-}
+   if (devinfo->gen < 6) {
+      brw_emit_depth_stencil_hiz(brw, depth_mt, depth_offset,
+                                 depthbuffer_format, depth_surface_type,
+                                 stencil_mt, hiz, separate_stencil,
+                                 width, height, tile_x, tile_y);
+      return;
+   }
 
-uint32_t
-brw_convert_depth_value(mesa_format format, float value)
-{
-   switch (format) {
-   case MESA_FORMAT_Z_FLOAT32:
-      return float_as_int(value);
-   case MESA_FORMAT_Z_UNORM16:
-      return value * ((1u << 16) - 1);
-   case MESA_FORMAT_Z24_UNORM_X8_UINT:
-      return value * ((1u << 24) - 1);
-   default:
-      unreachable("Invalid depth format");
+   /* Skip repeated NULL depth/stencil emits (think 2D rendering). */
+   if (!depth_mt && !stencil_mt && brw->no_depth_or_stencil) {
+      assert(brw->hw_ctx);
+      return;
+   }
+
+   brw_emit_depth_stall_flushes(brw);
+
+   const unsigned ds_dwords = brw->isl_dev.ds.size / 4;
+   intel_batchbuffer_begin(brw, ds_dwords, RENDER_RING);
+   uint32_t *ds_map = brw->batch.map_next;
+   const uint32_t ds_offset = (char *)ds_map - (char *)brw->batch.batch.map;
+
+   struct isl_view view = {
+      /* Some nice defaults */
+      .base_level = 0,
+      .levels = 1,
+      .base_array_layer = 0,
+      .array_len = 1,
+      .swizzle = ISL_SWIZZLE_IDENTITY,
+   };
+
+   struct isl_depth_stencil_hiz_emit_info info = {
+      .view = &view,
+   };
+
+   if (depth_mt) {
+      view.usage |= ISL_SURF_USAGE_DEPTH_BIT;
+      info.depth_surf = &depth_mt->surf;
+
+      info.depth_address =
+         brw_batch_reloc(&brw->batch,
+                         ds_offset + brw->isl_dev.ds.depth_offset,
+                         depth_mt->bo, depth_mt->offset, RELOC_WRITE);
+
+      info.mocs = brw_get_bo_mocs(devinfo, depth_mt->bo);
+      view.base_level = depth_irb->mt_level - depth_irb->mt->first_level;
+      view.base_array_layer = depth_irb->mt_layer;
+      view.array_len = MAX2(depth_irb->layer_count, 1);
+      view.format = depth_mt->surf.format;
+
+      info.hiz_usage = depth_mt->aux_usage;
+      if (!intel_renderbuffer_has_hiz(depth_irb)) {
+         /* Just because a miptree has ISL_AUX_USAGE_HIZ does not mean that
+          * all miplevels of that miptree are guaranteed to support HiZ.  See
+          * intel_miptree_level_enable_hiz for details.
+          */
+         info.hiz_usage = ISL_AUX_USAGE_NONE;
+      }
+
+      if (info.hiz_usage == ISL_AUX_USAGE_HIZ) {
+         info.hiz_surf = &depth_mt->aux_buf->surf;
+
+         uint32_t hiz_offset = 0;
+         if (devinfo->gen == 6) {
+            /* HiZ surfaces on Sandy Bridge technically don't support
+             * mip-mapping.  However, we can fake it by offsetting to the
+             * first slice of LOD0 in the HiZ surface.
+             */
+            isl_surf_get_image_offset_B_tile_sa(&depth_mt->aux_buf->surf,
+                                                view.base_level, 0, 0,
+                                                &hiz_offset, NULL, NULL);
+         }
+
+         info.hiz_address =
+            brw_batch_reloc(&brw->batch,
+                            ds_offset + brw->isl_dev.ds.hiz_offset,
+                            depth_mt->aux_buf->bo,
+                            depth_mt->aux_buf->offset + hiz_offset,
+                            RELOC_WRITE);
+      }
+
+      info.depth_clear_value = depth_mt->fast_clear_color.f32[0];
    }
+
+   if (stencil_mt) {
+      view.usage |= ISL_SURF_USAGE_STENCIL_BIT;
+      info.stencil_surf = &stencil_mt->surf;
+
+      if (!depth_mt) {
+         info.mocs = brw_get_bo_mocs(devinfo, stencil_mt->bo);
+         view.base_level = stencil_irb->mt_level - stencil_irb->mt->first_level;
+         view.base_array_layer = stencil_irb->mt_layer;
+         view.array_len = MAX2(stencil_irb->layer_count, 1);
+         view.format = stencil_mt->surf.format;
+      }
+
+      uint32_t stencil_offset = 0;
+      if (devinfo->gen == 6) {
+         /* Stencil surfaces on Sandy Bridge technically don't support
+          * mip-mapping.  However, we can fake it by offsetting to the
+          * first slice of LOD0 in the stencil surface.
+          */
+         isl_surf_get_image_offset_B_tile_sa(&stencil_mt->surf,
+                                             view.base_level, 0, 0,
+                                             &stencil_offset, NULL, NULL);
+      }
+
+      info.stencil_address =
+         brw_batch_reloc(&brw->batch,
+                         ds_offset + brw->isl_dev.ds.stencil_offset,
+                         stencil_mt->bo,
+                         stencil_mt->offset + stencil_offset,
+                         RELOC_WRITE);
+   }
+
+   isl_emit_depth_stencil_hiz_s(&brw->isl_dev, ds_map, &info);
+
+   brw->batch.map_next += ds_dwords;
+   intel_batchbuffer_advance(brw);
+
+   brw->no_depth_or_stencil = !depth_mt && !stencil_mt;
 }
 
-void
+static void
 brw_emit_depth_stencil_hiz(struct brw_context *brw,
                            struct intel_mipmap_tree *depth_mt,
                            uint32_t depth_offset, uint32_t depthbuffer_format,
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index f89182a0017..1b4745ef753 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -114,9 +114,6 @@ void brw_upload_invariant_state(struct brw_context *brw);
 uint32_t
 brw_depthbuffer_format(struct brw_context *brw);
 
-uint32_t
-brw_convert_depth_value(mesa_format format, float value);
-
 void brw_upload_state_base_address(struct brw_context *brw);
 
 /* gen8_depth_state.c */
diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c b/src/mesa/drivers/dri/i965/gen6_depth_state.c
deleted file mode 100644
index bca956e23d2..00000000000
--- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
+++ /dev/null
@@ -1,221 +0,0 @@
-/*
- * Copyright (c) 2014 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-
-#include "intel_batchbuffer.h"
-#include "intel_fbo.h"
-#include "intel_mipmap_tree.h"
-
-#include "brw_context.h"
-#include "brw_state.h"
-#include "brw_defines.h"
-
-#include "main/mtypes.h"
-#include "main/fbobject.h"
-#include "main/glformats.h"
-
-void
-gen6_emit_depth_stencil_hiz(struct brw_context *brw,
-                            struct intel_mipmap_tree *depth_mt,
-                            uint32_t depth_offset, uint32_t depthbuffer_format,
-                            uint32_t depth_surface_type,
-                            struct intel_mipmap_tree *stencil_mt,
-                            bool hiz, bool separate_stencil,
-                            uint32_t width, uint32_t height,
-                            uint32_t tile_x, uint32_t tile_y)
-{
-   struct gl_context *ctx = &brw->ctx;
-   struct gl_framebuffer *fb = ctx->DrawBuffer;
-   uint32_t surftype;
-   unsigned int depth = 1;
-   GLenum gl_target = GL_TEXTURE_2D;
-   unsigned int lod;
-   const struct intel_mipmap_tree *mt = depth_mt ? depth_mt : stencil_mt;
-   const struct intel_renderbuffer *irb = NULL;
-   const struct gl_renderbuffer *rb = NULL;
-
-   /* Enable the hiz bit if we're doing separate stencil, because it and the
-    * separate stencil bit must have the same value. From Section 2.11.5.6.1.1
-    * 3DSTATE_DEPTH_BUFFER, Bit 1.21 "Separate Stencil Enable":
-    *     [DevIL]: If this field is enabled, Hierarchical Depth Buffer
-    *     Enable must also be enabled.
-    *
-    *     [DevGT]: This field must be set to the same value (enabled or
-    *     disabled) as Hierarchical Depth Buffer Enable
-    */
-   bool enable_hiz_ss = hiz || separate_stencil;
-
-   brw_emit_depth_stall_flushes(brw);
-
-   irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
-   if (!irb)
-      irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
-   rb = (struct gl_renderbuffer*) irb;
-
-   if (rb) {
-      depth = MAX2(irb->layer_count, 1);
-      if (rb->TexImage)
-         gl_target = rb->TexImage->TexObject->Target;
-   }
-
-   switch (gl_target) {
-   case GL_TEXTURE_CUBE_MAP_ARRAY:
-   case GL_TEXTURE_CUBE_MAP:
-      /* The PRM claims that we should use BRW_SURFACE_CUBE for this
-       * situation, but experiments show that gl_Layer doesn't work when we do
-       * this.  So we use BRW_SURFACE_2D, since for rendering purposes this is
-       * equivalent.
-       */
-      surftype = BRW_SURFACE_2D;
-      depth *= 6;
-      break;
-   case GL_TEXTURE_3D:
-      assert(mt);
-      depth = mt->surf.logical_level0_px.depth;
-      /* fallthrough */
-   default:
-      surftype = translate_tex_target(gl_target);
-      break;
-   }
-
-   const unsigned min_array_element = irb ? irb->mt_layer : 0;
-
-   lod = irb ? irb->mt_level - irb->mt->first_level : 0;
-
-   if (mt) {
-      width = mt->surf.logical_level0_px.width;
-      height = mt->surf.logical_level0_px.height;
-   }
-
-   BEGIN_BATCH(7);
-   /* 3DSTATE_DEPTH_BUFFER dw0 */
-   OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
-
-   /* 3DSTATE_DEPTH_BUFFER dw1 */
-   OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) |
-             (depthbuffer_format << 18) |
-             ((enable_hiz_ss ? 1 : 0) << 21) | /* separate stencil enable */
-             ((enable_hiz_ss ? 1 : 0) << 22) | /* hiz enable */
-             (BRW_TILEWALK_YMAJOR << 26) |
-             (1 << 27) |
-             (surftype << 29));
-
-   /* 3DSTATE_DEPTH_BUFFER dw2 */
-   if (depth_mt) {
-      OUT_RELOC(depth_mt->bo, RELOC_WRITE, 0);
-   } else {
-      OUT_BATCH(0);
-   }
-
-   /* 3DSTATE_DEPTH_BUFFER dw3 */
-   OUT_BATCH(((width - 1) << 6) |
-             ((height - 1) << 19) |
-             lod << 2);
-
-   /* 3DSTATE_DEPTH_BUFFER dw4 */
-   OUT_BATCH((depth - 1) << 21 |
-             min_array_element << 10 |
-             (depth - 1) << 1);
-
-   /* 3DSTATE_DEPTH_BUFFER dw5 */
-   OUT_BATCH(0);
-   assert(tile_x == 0 && tile_y == 0);
-
-   /* 3DSTATE_DEPTH_BUFFER dw6 */
-   OUT_BATCH(0);
-
-   ADVANCE_BATCH();
-
-   if (hiz || separate_stencil) {
-      /*
-       * In the 3DSTATE_DEPTH_BUFFER batch emitted above, the 'separate
-       * stencil enable' and 'hiz enable' bits were set. Therefore we must
-       * emit 3DSTATE_HIER_DEPTH_BUFFER and 3DSTATE_STENCIL_BUFFER. Even if
-       * there is no stencil buffer, 3DSTATE_STENCIL_BUFFER must be emitted;
-       * failure to do so causes hangs on gen5 and a stall on gen6.
-       */
-
-      /* Emit stencil buffer. */
-      if (separate_stencil) {
-         assert(stencil_mt->format == MESA_FORMAT_S_UINT8);
-         assert(stencil_mt->surf.size > 0);
-
-         uint32_t offset;
-         isl_surf_get_image_offset_B_tile_sa(&stencil_mt->surf,
-                                             lod, 0, 0, &offset, NULL, NULL);
-
-	 BEGIN_BATCH(3);
-	 OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
-	 OUT_BATCH(stencil_mt->surf.row_pitch - 1);
-	 OUT_RELOC(stencil_mt->bo, RELOC_WRITE, offset);
-	 ADVANCE_BATCH();
-      } else {
-	 BEGIN_BATCH(3);
-	 OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
-	 OUT_BATCH(0);
-	 OUT_BATCH(0);
-	 ADVANCE_BATCH();
-      }
-
-      /* Emit hiz buffer. */
-      if (hiz) {
-         assert(depth_mt);
-
-         uint32_t offset;
-         isl_surf_get_image_offset_B_tile_sa(&depth_mt->aux_buf->surf,
-                                             lod, 0, 0, &offset, NULL, NULL);
-
-	 BEGIN_BATCH(3);
-	 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
-	 OUT_BATCH(depth_mt->aux_buf->surf.row_pitch - 1);
-	 OUT_RELOC(depth_mt->aux_buf->bo, RELOC_WRITE, offset);
-	 ADVANCE_BATCH();
-      } else {
-	 BEGIN_BATCH(3);
-	 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
-	 OUT_BATCH(0);
-	 OUT_BATCH(0);
-	 ADVANCE_BATCH();
-      }
-   }
-
-   /*
-    * On Gen >= 6, emit clear params for safety. If using hiz, then clear
-    * params must be emitted.
-    *
-    * From Section 2.11.5.6.4.1 3DSTATE_CLEAR_PARAMS:
-    *     3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE packet
-    *     when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
-    */
-   BEGIN_BATCH(2);
-   OUT_BATCH(_3DSTATE_CLEAR_PARAMS << 16 |
-             GEN5_DEPTH_CLEAR_VALID |
-             (2 - 2));
-   if (depth_mt) {
-      OUT_BATCH(brw_convert_depth_value(depth_mt->format,
-                                        depth_mt->fast_clear_color.f32[0]));
-   } else {
-      OUT_BATCH(0);
-   }
-   ADVANCE_BATCH();
-}
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c
deleted file mode 100644
index 5c88cf55fa0..00000000000
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
- * Copyright © 2011 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-#include "main/mtypes.h"
-#include "intel_batchbuffer.h"
-#include "intel_mipmap_tree.h"
-#include "intel_fbo.h"
-#include "brw_context.h"
-#include "brw_state.h"
-#include "brw_defines.h"
-
-void
-gen7_emit_depth_stencil_hiz(struct brw_context *brw,
-                            struct intel_mipmap_tree *depth_mt,
-                            uint32_t depth_offset, uint32_t depthbuffer_format,
-                            uint32_t depth_surface_type,
-                            struct intel_mipmap_tree *stencil_mt,
-                            bool hiz, bool separate_stencil,
-                            uint32_t width, uint32_t height,
-                            uint32_t tile_x, uint32_t tile_y)
-{
-   const struct gen_device_info *devinfo = &brw->screen->devinfo;
-   struct gl_context *ctx = &brw->ctx;
-   const uint8_t mocs = GEN7_MOCS_L3;
-   struct gl_framebuffer *fb = ctx->DrawBuffer;
-   uint32_t surftype;
-   unsigned int depth = 1;
-   unsigned int min_array_element;
-   GLenum gl_target = GL_TEXTURE_2D;
-   unsigned int lod;
-   const struct intel_mipmap_tree *mt = depth_mt ? depth_mt : stencil_mt;
-   const struct intel_renderbuffer *irb = NULL;
-   const struct gl_renderbuffer *rb = NULL;
-
-   /* Skip repeated NULL depth/stencil emits (think 2D rendering). */
-   if (!mt && brw->no_depth_or_stencil) {
-      assert(brw->hw_ctx);
-      return;
-   }
-
-   brw_emit_depth_stall_flushes(brw);
-
-   irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
-   if (!irb)
-      irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
-   rb = (struct gl_renderbuffer*) irb;
-
-   if (rb) {
-      depth = MAX2(irb->layer_count, 1);
-      if (rb->TexImage)
-         gl_target = rb->TexImage->TexObject->Target;
-   }
-
-   switch (gl_target) {
-   case GL_TEXTURE_CUBE_MAP_ARRAY:
-   case GL_TEXTURE_CUBE_MAP:
-      /* The PRM claims that we should use BRW_SURFACE_CUBE for this
-       * situation, but experiments show that gl_Layer doesn't work when we do
-       * this.  So we use BRW_SURFACE_2D, since for rendering purposes this is
-       * equivalent.
-       */
-      surftype = BRW_SURFACE_2D;
-      depth *= 6;
-      break;
-   case GL_TEXTURE_3D:
-      assert(mt);
-      depth = mt->surf.logical_level0_px.depth;
-      /* fallthrough */
-   default:
-      surftype = translate_tex_target(gl_target);
-      break;
-   }
-
-   min_array_element = irb ? irb->mt_layer : 0;
-
-   lod = irb ? irb->mt_level - irb->mt->first_level : 0;
-
-   if (mt) {
-      width = mt->surf.logical_level0_px.width;
-      height = mt->surf.logical_level0_px.height;
-   }
-
-   /* _NEW_DEPTH, _NEW_STENCIL, _NEW_BUFFERS */
-   BEGIN_BATCH(7);
-   /* 3DSTATE_DEPTH_BUFFER dw0 */
-   OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
-
-   /* 3DSTATE_DEPTH_BUFFER dw1 */
-   OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) |
-             (depthbuffer_format << 18) |
-             ((hiz ? 1 : 0) << 22) |
-             ((stencil_mt != NULL) << 27) | /* Stencil Write Enable */
-             ((depth_mt != NULL) << 28) | /* Depth Write Enable */
-             (surftype << 29));
-
-   /* 3DSTATE_DEPTH_BUFFER dw2 */
-   if (depth_mt) {
-      OUT_RELOC(depth_mt->bo, RELOC_WRITE, 0);
-   } else {
-      OUT_BATCH(0);
-   }
-
-   /* 3DSTATE_DEPTH_BUFFER dw3 */
-   OUT_BATCH(((width - 1) << 4) |
-             ((height - 1) << 18) |
-             lod);
-
-   /* 3DSTATE_DEPTH_BUFFER dw4 */
-   OUT_BATCH(((depth - 1) << 21) |
-             (min_array_element << 10) |
-             mocs);
-
-   /* 3DSTATE_DEPTH_BUFFER dw5 */
-   OUT_BATCH(0);
-
-   /* 3DSTATE_DEPTH_BUFFER dw6 */
-   OUT_BATCH((depth - 1) << 21);
-   ADVANCE_BATCH();
-
-   if (stencil_mt == NULL) {
-      BEGIN_BATCH(3);
-      OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
-      OUT_BATCH(0);
-      OUT_BATCH(0);
-      ADVANCE_BATCH();
-   } else {
-      stencil_mt->r8stencil_needs_update = true;
-      const int enabled = devinfo->is_haswell ? HSW_STENCIL_ENABLED : 0;
-
-      BEGIN_BATCH(3);
-      OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
-      OUT_BATCH(enabled |
-                mocs << 25 |
-	        (stencil_mt->surf.row_pitch - 1));
-      OUT_RELOC(stencil_mt->bo, RELOC_WRITE, 0);
-      ADVANCE_BATCH();
-   }
-
-   if (!hiz) {
-      BEGIN_BATCH(3);
-      OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
-      OUT_BATCH(0);
-      OUT_BATCH(0);
-      ADVANCE_BATCH();
-   } else {
-      assert(depth_mt);
-
-      BEGIN_BATCH(3);
-      OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
-      OUT_BATCH((mocs << 25) |
-                (depth_mt->aux_buf->pitch - 1));
-      OUT_RELOC(depth_mt->aux_buf->bo, RELOC_WRITE, 0);
-      ADVANCE_BATCH();
-   }
-
-   BEGIN_BATCH(3);
-   OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
-   if (depth_mt) {
-      OUT_BATCH(brw_convert_depth_value(depth_mt->format,
-                                        depth_mt->fast_clear_color.f32[0]));
-   } else {
-      OUT_BATCH(0);
-   }
-   OUT_BATCH(1);
-   ADVANCE_BATCH();
-
-   brw->no_depth_or_stencil = !mt;
-}
diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index a00e22a6868..1ea5884f818 100644
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -32,181 +32,6 @@
 #include "main/framebuffer.h"
 
 /**
- * Helper function to emit depth related command packets.
- */
-static void
-emit_depth_packets(struct brw_context *brw,
-                   struct intel_mipmap_tree *depth_mt,
-                   uint32_t depthbuffer_format,
-                   uint32_t depth_surface_type,
-                   struct intel_mipmap_tree *stencil_mt,
-                   bool hiz,
-                   uint32_t width,
-                   uint32_t height,
-                   uint32_t depth,
-                   uint32_t lod,
-                   uint32_t min_array_element)
-{
-   const struct gen_device_info *devinfo = &brw->screen->devinfo;
-   uint32_t mocs_wb = devinfo->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
-
-   /* Skip repeated NULL depth/stencil emits (think 2D rendering). */
-   if (!depth_mt && !stencil_mt && brw->no_depth_or_stencil) {
-      assert(brw->hw_ctx);
-      return;
-   }
-
-   brw_emit_depth_stall_flushes(brw);
-
-   /* _NEW_BUFFERS, _NEW_DEPTH, _NEW_STENCIL */
-   BEGIN_BATCH(8);
-   OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (8 - 2));
-   OUT_BATCH(depth_surface_type << 29 |
-             (depth_mt != NULL) << 28 | /* Depth Write Enable */
-             (stencil_mt != NULL) << 27 | /* Stencil Write Enable */
-             (hiz ? 1 : 0) << 22 |
-             depthbuffer_format << 18 |
-             (depth_mt ? depth_mt->surf.row_pitch - 1 : 0));
-   if (depth_mt) {
-      OUT_RELOC64(depth_mt->bo, RELOC_WRITE, 0);
-   } else {
-      OUT_BATCH(0);
-      OUT_BATCH(0);
-   }
-   OUT_BATCH(((width - 1) << 4) | ((height - 1) << 18) | lod);
-   OUT_BATCH(((depth - 1) << 21) | (min_array_element << 10) | mocs_wb);
-   OUT_BATCH(0);
-   OUT_BATCH(((depth - 1) << 21) |
-              (depth_mt ? depth_mt->surf.array_pitch_el_rows >> 2 : 0));
-   ADVANCE_BATCH();
-
-   if (stencil_mt == NULL) {
-      BEGIN_BATCH(5);
-      OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (5 - 2));
-      OUT_BATCH(0);
-      OUT_BATCH(0);
-      OUT_BATCH(0);
-      OUT_BATCH(0);
-      ADVANCE_BATCH();
-   } else {
-      BEGIN_BATCH(5);
-      OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (5 - 2));
-      OUT_BATCH(HSW_STENCIL_ENABLED | mocs_wb << 22 |
-                (stencil_mt->surf.row_pitch - 1));
-      OUT_RELOC64(stencil_mt->bo, RELOC_WRITE, 0);
-      OUT_BATCH(stencil_mt->surf.array_pitch_el_rows >> 2);
-      ADVANCE_BATCH();
-   }
-
-   if (!hiz) {
-      BEGIN_BATCH(5);
-      OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2));
-      OUT_BATCH(0);
-      OUT_BATCH(0);
-      OUT_BATCH(0);
-      OUT_BATCH(0);
-      ADVANCE_BATCH();
-   } else {
-      assert(depth_mt);
-      BEGIN_BATCH(5);
-      OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2));
-      OUT_BATCH((depth_mt->aux_buf->pitch - 1) | mocs_wb << 25);
-      OUT_RELOC64(depth_mt->aux_buf->bo, RELOC_WRITE, 0);
-      OUT_BATCH(depth_mt->aux_buf->qpitch >> 2);
-      ADVANCE_BATCH();
-   }
-
-   BEGIN_BATCH(3);
-   OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
-   OUT_BATCH(depth_mt ? depth_mt->fast_clear_color.u32[0] : 0);
-   OUT_BATCH(1);
-   ADVANCE_BATCH();
-
-   brw->no_depth_or_stencil = !depth_mt && !stencil_mt;
-}
-
-/* Awful vtable-compatible function; should be cleaned up in the future. */
-void
-gen8_emit_depth_stencil_hiz(struct brw_context *brw,
-                            struct intel_mipmap_tree *depth_mt,
-                            uint32_t depth_offset,
-                            uint32_t depthbuffer_format,
-                            uint32_t depth_surface_type,
-                            struct intel_mipmap_tree *stencil_mt,
-                            bool hiz, bool separate_stencil,
-                            uint32_t width, uint32_t height,
-                            uint32_t tile_x, uint32_t tile_y)
-{
-   const struct gen_device_info *devinfo = &brw->screen->devinfo;
-   struct gl_context *ctx = &brw->ctx;
-   struct gl_framebuffer *fb = ctx->DrawBuffer;
-   uint32_t surftype;
-   unsigned int depth = 1;
-   unsigned int min_array_element;
-   GLenum gl_target = GL_TEXTURE_2D;
-   unsigned int lod;
-   const struct intel_mipmap_tree *mt = depth_mt ? depth_mt : stencil_mt;
-   const struct intel_renderbuffer *irb = NULL;
-   const struct gl_renderbuffer *rb = NULL;
-
-   irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
-   if (!irb)
-      irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
-   rb = (struct gl_renderbuffer *) irb;
-
-   if (rb) {
-      depth = MAX2(irb->layer_count, 1);
-      if (rb->TexImage)
-         gl_target = rb->TexImage->TexObject->Target;
-   }
-
-   switch (gl_target) {
-   case GL_TEXTURE_CUBE_MAP_ARRAY:
-   case GL_TEXTURE_CUBE_MAP:
-      /* The PRM claims that we should use BRW_SURFACE_CUBE for this
-       * situation, but experiments show that gl_Layer doesn't work when we do
-       * this.  So we use BRW_SURFACE_2D, since for rendering purposes this is
-       * equivalent.
-       */
-      surftype = BRW_SURFACE_2D;
-      depth *= 6;
-      break;
-   case GL_TEXTURE_3D:
-      assert(mt);
-      depth = mt->surf.logical_level0_px.depth;
-      surftype = translate_tex_target(gl_target);
-      break;
-   case GL_TEXTURE_1D_ARRAY:
-   case GL_TEXTURE_1D:
-      if (devinfo->gen >= 9) {
-         /* WaDisable1DDepthStencil. Skylake+ doesn't support 1D depth
-          * textures but it does allow pretending it's a 2D texture
-          * instead.
-          */
-         surftype = BRW_SURFACE_2D;
-         break;
-      }
-      /* fallthrough */
-   default:
-      surftype = translate_tex_target(gl_target);
-      break;
-   }
-
-   min_array_element = irb ? irb->mt_layer : 0;
-
-   lod = irb ? irb->mt_level - irb->mt->first_level : 0;
-
-   if (mt) {
-      width = mt->surf.logical_level0_px.width;
-      height = mt->surf.logical_level0_px.height;
-   }
-
-   emit_depth_packets(brw, depth_mt, brw_depthbuffer_format(brw), surftype,
-                      stencil_mt,
-                      hiz, width, height, depth, lod, min_array_element);
-}
-
-/**
  * Should we set the PMA FIX ENABLE bit?
  *
  * To avoid unnecessary depth related stalls, we need to set this bit.
diff --git a/src/mesa/drivers/dri/i965/meson.build b/src/mesa/drivers/dri/i965/meson.build
index a2c1896fecb..20404d5b059 100644
--- a/src/mesa/drivers/dri/i965/meson.build
+++ b/src/mesa/drivers/dri/i965/meson.build
@@ -87,14 +87,12 @@ files_i965 = files(
   'gen4_blorp_exec.h',
   'gen6_clip_state.c',
   'gen6_constant_state.c',
-  'gen6_depth_state.c',
   'gen6_multisample_state.c',
   'gen6_queryobj.c',
   'gen6_sampler_state.c',
   'gen6_sol.c',
   'gen6_urb.c',
   'gen7_l3_state.c',
-  'gen7_misc_state.c',
   'gen7_sol_state.c',
   'gen7_urb.c',
   'gen8_depth_state.c',