diff options
| author | Eric Anholt <[email protected]> | 2015-03-23 16:34:24 -0700 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2015-03-24 10:39:12 -0700 |
| commit | b3ea377f8629ada57c67632a89f0d2e9d2faf23c (patch) | |
| tree | d7599d22aba757255c043de44bb6a9674ec4f6b1 | |
| parent | 8975a09494cb6ee7b010fddb0ca5a7a74d46b0c7 (diff) | |
vc4: Write the alignment of level width consistently in validation.
16 / cpp happens to be the same as utile_w on the only raster format
supported (4 bytes per pixel), but simulator/hw source code generally
talks in terms of utiles.
| -rw-r--r-- | src/gallium/drivers/vc4/kernel/vc4_validate.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/gallium/drivers/vc4/kernel/vc4_validate.c b/src/gallium/drivers/vc4/kernel/vc4_validate.c index 0691a8d769c..568b625e64b 100644 --- a/src/gallium/drivers/vc4/kernel/vc4_validate.c +++ b/src/gallium/drivers/vc4/kernel/vc4_validate.c @@ -164,7 +164,7 @@ check_tex_size(struct vc4_exec_info *exec, struct drm_gem_cma_object *fbo, switch (tiling_format) { case VC4_TILING_FORMAT_LINEAR: - aligned_width = roundup(width, 16 / cpp); + aligned_width = roundup(width, utile_w); aligned_height = height; break; case VC4_TILING_FORMAT_T: @@ -951,7 +951,7 @@ reloc_tex(struct vc4_exec_info *exec, aligned_height = roundup(level_height, utile_h); break; default: - aligned_width = roundup(level_width, 16 / cpp); + aligned_width = roundup(level_width, utile_w); aligned_height = level_height; break; } |