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authorAlex Deucher <[email protected]>2010-08-16 11:34:17 -0400
committerAlex Deucher <[email protected]>2010-08-16 11:34:17 -0400
commit5ff769b21d39c8f78c309351aca5869eda0ccba3 (patch)
tree8050c907e00aa3432cccb839151c56ae3086cf32
parentf201217c1d87919572a3b1cf7de94f580f20e5f0 (diff)
r600c: blit emit updates
- set VGT_MAX_VTX_INDX to a larger value - emit PA_SC_AA_CONFIG. The command checker in 2.6.36+ requires this reg.
-rw-r--r--src/mesa/drivers/dri/r600/r600_blit.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/r600/r600_blit.c b/src/mesa/drivers/dri/r600/r600_blit.c
index 27acff9c166..4fd425b8094 100644
--- a/src/mesa/drivers/dri/r600/r600_blit.c
+++ b/src/mesa/drivers/dri/r600/r600_blit.c
@@ -1499,9 +1499,10 @@ set_default_state(context_t *context)
R600_OUT_BATCH_REGVAL(PA_SU_VTX_CNTL, (PIX_CENTER_bit) |
(X_ROUND_TO_EVEN << PA_SU_VTX_CNTL__ROUND_MODE_shift) |
(X_1_256TH << QUANT_MODE_shift));
+ R600_OUT_BATCH_REGVAL(PA_SC_AA_CONFIG, 0);
R600_OUT_BATCH_REGSEQ(VGT_MAX_VTX_INDX, 4);
- R600_OUT_BATCH(2048);
+ R600_OUT_BATCH(0xffffff);
R600_OUT_BATCH(0);
R600_OUT_BATCH(0);
R600_OUT_BATCH(0);
@@ -1614,7 +1615,7 @@ unsigned r600_blit(GLcontext *ctx,
/* Flush is needed to make sure that source buffer has correct data */
radeonFlush(ctx);
- rcommonEnsureCmdBufSpace(&context->radeon, 308, __FUNCTION__);
+ rcommonEnsureCmdBufSpace(&context->radeon, 311, __FUNCTION__);
/* load shaders */
load_shaders(context->radeon.glCtx);
@@ -1623,7 +1624,7 @@ unsigned r600_blit(GLcontext *ctx,
return GL_FALSE;
/* set clear state */
- /* 117 */
+ /* 120 */
set_default_state(context);
/* shaders */