diff options
| author | Gert Wollny <[email protected]> | 2019-04-07 08:33:34 +0200 |
|---|---|---|
| committer | Gert Wollny <[email protected]> | 2019-04-09 08:17:44 +0000 |
| commit | 47dd7c40544e00888ca8942af2914b2fcdcd94f0 (patch) | |
| tree | d05eb8d75e979581e372dcf4b57c7ea4429dfd7c | |
| parent | 11f219a5ee8a80376a892d5ef4c7d46a76232cb8 (diff) | |
softpipe: raise number of bits used for X coordinate texture lookup
With buffers the addressing is done on a per byte basis and we with
a maximal block size of 16 byte we have to take into acount four more
bits. For simplicity just remove the TEX_TILE_SIZE_LOG2, which is 5 bit.
Signed-off-by: Gert Wollny <[email protected]>
Reviewed-by: Dave Airlie <[email protected]>
| -rw-r--r-- | src/gallium/drivers/softpipe/sp_tex_tile_cache.c | 2 | ||||
| -rw-r--r-- | src/gallium/drivers/softpipe/sp_tex_tile_cache.h | 11 |
2 files changed, 6 insertions, 7 deletions
diff --git a/src/gallium/drivers/softpipe/sp_tex_tile_cache.c b/src/gallium/drivers/softpipe/sp_tex_tile_cache.c index 8fbc972aa85..e510ac58c06 100644 --- a/src/gallium/drivers/softpipe/sp_tex_tile_cache.c +++ b/src/gallium/drivers/softpipe/sp_tex_tile_cache.c @@ -50,7 +50,7 @@ sp_create_tex_tile_cache( struct pipe_context *pipe ) uint pos; /* make sure max texture size works */ - assert((TEX_TILE_SIZE << TEX_ADDR_BITS) >= (1 << (SP_MAX_TEXTURE_2D_LEVELS-1))); + assert((TEX_TILE_SIZE << TEX_Y_BITS) >= (1 << (SP_MAX_TEXTURE_2D_LEVELS-1))); tc = CALLOC_STRUCT( softpipe_tex_tile_cache ); if (tc) { diff --git a/src/gallium/drivers/softpipe/sp_tex_tile_cache.h b/src/gallium/drivers/softpipe/sp_tex_tile_cache.h index b7ad222d715..2e4635f3811 100644 --- a/src/gallium/drivers/softpipe/sp_tex_tile_cache.h +++ b/src/gallium/drivers/softpipe/sp_tex_tile_cache.h @@ -43,18 +43,17 @@ struct softpipe_tex_tile_cache; #define TEX_TILE_SIZE_LOG2 5 #define TEX_TILE_SIZE (1 << TEX_TILE_SIZE_LOG2) - -#define TEX_ADDR_BITS (SP_MAX_TEXTURE_2D_LEVELS - 1 - TEX_TILE_SIZE_LOG2) -#define TEX_Z_BITS (SP_MAX_TEXTURE_2D_LEVELS - 1) +#define TEX_ADDR_BITS (SP_MAX_TEXTURE_2D_LEVELS - 1) +#define TEX_Y_BITS (SP_MAX_TEXTURE_2D_LEVELS - 1 - TEX_TILE_SIZE_LOG2) /** * Texture tile address as a union for fast compares. */ union tex_tile_address { struct { - unsigned x:TEX_ADDR_BITS; /* 16K / TILE_SIZE */ - unsigned y:TEX_ADDR_BITS; /* 16K / TILE_SIZE */ - unsigned z:TEX_Z_BITS; /* 16K -- z not tiled */ + unsigned x:TEX_ADDR_BITS; /* 16K -- need extra bits for texture buffers */ + unsigned y:TEX_Y_BITS; /* 16K / TILE_SIZE */ + unsigned z:TEX_ADDR_BITS; /* 16K -- z not tiled */ unsigned level:4; unsigned invalid:1; } bits; |