diff options
author | Nanley Chery <[email protected]> | 2019-04-26 16:52:48 -0700 |
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committer | Nanley Chery <[email protected]> | 2019-05-14 16:23:12 +0000 |
commit | 1de089797c2eb15a6eb7e1af63a97ca8e6db7c92 (patch) | |
tree | c14c5585a7177de3d3d1d358ba8ff009d3de9587 | |
parent | cf758c41827d959e62953284c520807e2d281e86 (diff) |
isl: Modify restrictions in isl_surf_get_mcs_surf()
Import some restrictions from intel_miptree_supports_mcs() and don't
assume that the caller knows which device generations are supported.
Reviewed-by: Rafael Antognolli <[email protected]>
-rw-r--r-- | src/intel/isl/isl.c | 24 |
1 files changed, 19 insertions, 5 deletions
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index acfed5119ba..cbc12955020 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -1686,16 +1686,30 @@ isl_surf_get_mcs_surf(const struct isl_device *dev, const struct isl_surf *surf, struct isl_surf *mcs_surf) { - assert(ISL_DEV_GEN(dev) >= 7); - - /* It must be multisampled with an array layout */ - assert(surf->samples > 1 && surf->msaa_layout == ISL_MSAA_LAYOUT_ARRAY); - /* The following are true of all multisampled surfaces */ + assert(surf->samples > 1); assert(surf->dim == ISL_SURF_DIM_2D); assert(surf->levels == 1); assert(surf->logical_level0_px.depth == 1); + /* It must be multisampled with an array layout */ + if (surf->msaa_layout != ISL_MSAA_LAYOUT_ARRAY) + return false; + + /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"): + * + * This field must be set to 0 for all SINT MSRTs when all RT channels + * are not written + * + * In practice this means that we have to disable MCS for all signed + * integer MSAA buffers. The alternative, to disable MCS only when one + * of the render target channels is disabled, is impractical because it + * would require converting between CMS and UMS MSAA layouts on the fly, + * which is expensive. + */ + if (ISL_DEV_GEN(dev) == 7 && isl_format_has_sint_channel(surf->format)) + return false; + /* The "Auxiliary Surface Pitch" field in RENDER_SURFACE_STATE is only 9 * bits which means the maximum pitch of a compression surface is 512 * tiles or 64KB (since MCS is always Y-tiled). Since a 16x MCS buffer is |