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authorEric Anholt <[email protected]>2010-10-04 15:07:17 -0700
committerEric Anholt <[email protected]>2010-10-04 16:08:17 -0700
commitea909be58dda7e916cb9ce434ecb78597881ad33 (patch)
treeeaf4bc2e364d6622a401587a56ea92f5c63c2501
parent739aec39bd25e79adce306d6cf48296b7c9e4fc0 (diff)
i965: Add support for gen6 FB writes to the new FS.
This uses message headers for now, since we'll need it for MRT. We can cut out the header later.
-rw-r--r--src/mesa/drivers/dri/i965/brw_eu_emit.c11
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs.cpp14
2 files changed, 22 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 09cc8b2bd5e..59541353214 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -448,6 +448,7 @@ static void brw_set_dp_write_message( struct brw_context *brw,
GLuint msg_control,
GLuint msg_type,
GLuint msg_length,
+ GLboolean header_present,
GLuint pixel_scoreboard_clear,
GLuint response_length,
GLuint end_of_thread,
@@ -462,7 +463,7 @@ static void brw_set_dp_write_message( struct brw_context *brw,
insn->bits3.dp_render_cache.pixel_scoreboard_clear = pixel_scoreboard_clear;
insn->bits3.dp_render_cache.msg_type = msg_type;
insn->bits3.dp_render_cache.send_commit_msg = send_commit_msg;
- insn->bits3.dp_render_cache.header_present = 0; /* XXX */
+ insn->bits3.dp_render_cache.header_present = header_present;
insn->bits3.dp_render_cache.response_length = response_length;
insn->bits3.dp_render_cache.msg_length = msg_length;
insn->bits3.dp_render_cache.end_of_thread = end_of_thread;
@@ -476,7 +477,7 @@ static void brw_set_dp_write_message( struct brw_context *brw,
insn->bits3.dp_write_gen5.pixel_scoreboard_clear = pixel_scoreboard_clear;
insn->bits3.dp_write_gen5.msg_type = msg_type;
insn->bits3.dp_write_gen5.send_commit_msg = send_commit_msg;
- insn->bits3.dp_write_gen5.header_present = 1;
+ insn->bits3.dp_write_gen5.header_present = header_present;
insn->bits3.dp_write_gen5.response_length = response_length;
insn->bits3.dp_write_gen5.msg_length = msg_length;
insn->bits3.dp_write_gen5.end_of_thread = end_of_thread;
@@ -1293,6 +1294,7 @@ void brw_dp_WRITE_16( struct brw_compile *p,
BRW_DATAPORT_OWORD_BLOCK_4_OWORDS, /* msg_control */
BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE, /* msg_type */
msg_length,
+ GL_TRUE, /* header_present */
0, /* pixel scoreboard */
send_commit_msg, /* response_length */
0, /* eot */
@@ -1530,12 +1532,16 @@ void brw_fb_WRITE(struct brw_compile *p,
struct intel_context *intel = &p->brw->intel;
struct brw_instruction *insn;
GLuint msg_control, msg_type;
+ GLboolean header_present = GL_TRUE;
insn = next_insn(p, BRW_OPCODE_SEND);
insn->header.predicate_control = 0; /* XXX */
insn->header.compression_control = BRW_COMPRESSION_NONE;
if (intel->gen >= 6) {
+ if (msg_length == 4)
+ header_present = GL_FALSE;
+
/* headerless version, just submit color payload */
src0 = brw_message_reg(msg_reg_nr);
@@ -1559,6 +1565,7 @@ void brw_fb_WRITE(struct brw_compile *p,
msg_control,
msg_type,
msg_length,
+ header_present,
1, /* pixel scoreboard */
response_length,
eot,
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 5eaa9984476..f42c4696410 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -1920,6 +1920,7 @@ void
fs_visitor::generate_fb_write(fs_inst *inst)
{
GLboolean eot = inst->eot;
+ struct brw_reg implied_header;
/* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
* move, here's g1.
@@ -1927,16 +1928,27 @@ fs_visitor::generate_fb_write(fs_inst *inst)
brw_push_insn_state(p);
brw_set_mask_control(p, BRW_MASK_DISABLE);
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
+
+ if (intel->gen >= 6) {
+ brw_MOV(p,
+ brw_message_reg(0),
+ brw_vec8_grf(0, 0));
+ implied_header = brw_null_reg();
+ } else {
+ implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
+ }
+
brw_MOV(p,
brw_message_reg(1),
brw_vec8_grf(1, 0));
+
brw_pop_insn_state(p);
brw_fb_WRITE(p,
8, /* dispatch_width */
retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW),
0, /* base MRF */
- retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW),
+ implied_header,
inst->target,
inst->mlen,
0,