diff options
| author | Christian König <[email protected]> | 2011-05-15 19:26:53 +0200 |
|---|---|---|
| committer | Christian König <[email protected]> | 2011-05-15 19:26:53 +0200 |
| commit | 828540e491d88b9b6217e6568873a78462919ae8 (patch) | |
| tree | c952145c1188cdf6b9c56902f8f5c189e090c278 | |
| parent | 3db6514357a7c634045ae7bc7bba7d7dbf9d58c5 (diff) | |
| parent | bd5b7a6f7113da38a2c1f07a4a71e9993666a567 (diff) | |
Merge remote-tracking branch 'origin/master' into pipe-video
102 files changed, 3128 insertions, 1288 deletions
diff --git a/configure.ac b/configure.ac index 70c84b76cac..e7eca3ce453 100644 --- a/configure.ac +++ b/configure.ac @@ -1194,12 +1194,12 @@ if test "x$enable_egl" = xyes; then EGL_DRIVERS_DIRS="glx" fi + PKG_CHECK_MODULES([LIBUDEV], [libudev > 150], + [have_libudev=yes],[have_libudev=no]) if test "$mesa_driver" = dri; then # build egl_dri2 when xcb-dri2 is available PKG_CHECK_MODULES([XCB_DRI2], [x11-xcb xcb-dri2 xcb-xfixes], [have_xcb_dri2=yes],[have_xcb_dri2=no]) - PKG_CHECK_MODULES([LIBUDEV], [libudev > 150], - [have_libudev=yes],[have_libudev=no]) if test "$have_xcb_dri2" = yes; then EGL_DRIVER_DRI2=dri2 diff --git a/docs/relnotes-7.11.html b/docs/relnotes-7.11.html index 1c22b082e2d..f2ff9c7c587 100644 --- a/docs/relnotes-7.11.html +++ b/docs/relnotes-7.11.html @@ -45,6 +45,7 @@ tbd <li>GL_ARB_robustness (all drivers) <li>GL_ARB_sampler_objects (gallium drivers) <li>GL_ARB_seamless_cube_map (gallium r600) +<li>GL_ARB_shader_texture_lod (gallium drivers) <li>GL_ARB_sync (gallium drivers only, intel support was in 7.6) <li>GL_ARB_texture_compression_rgtc (gallium drivers, swrast, i965) <li>GL_ARB_texture_float (gallium, i965) diff --git a/include/GL/glu.h b/include/GL/glu.h index cd967ac5ed4..ba2228d8d86 100644 --- a/include/GL/glu.h +++ b/include/GL/glu.h @@ -284,7 +284,7 @@ typedef GLUtesselator GLUtriangulatorObj; #define GLU_TESS_MAX_COORD 1.0e150 /* Internal convenience typedefs */ -typedef void (GLAPIENTRYP _GLUfuncptr)(); +typedef void (GLAPIENTRYP _GLUfuncptr)(void); GLAPI void GLAPIENTRY gluBeginCurve (GLUnurbs* nurb); GLAPI void GLAPIENTRY gluBeginPolygon (GLUtesselator* tess); diff --git a/src/egl/drivers/dri2/Makefile b/src/egl/drivers/dri2/Makefile index 4783975852a..447babd6747 100644 --- a/src/egl/drivers/dri2/Makefile +++ b/src/egl/drivers/dri2/Makefile @@ -4,18 +4,17 @@ TOP = ../../../.. include $(TOP)/configs/current EGL_DRIVER = egl_dri2 -EGL_SOURCES = egl_dri2.c platform_x11.c platform_drm.c +EGL_SOURCES = egl_dri2.c platform_drm.c EGL_INCLUDES = \ -I$(TOP)/include \ -I$(TOP)/src/egl/main \ -I$(TOP)/src/mapi \ -DDEFAULT_DRIVER_DIR=\"$(DRI_DRIVER_SEARCH_DIR)\" \ - $(XCB_DRI2_CFLAGS) \ $(LIBUDEV_CFLAGS) \ $(LIBDRM_CFLAGS) -EGL_LIBS = $(XCB_DRI2_LIBS) $(LIBUDEV_LIBS) $(DLOPEN_LIBS) $(LIBDRM_LIB) +EGL_LIBS = $(LIBUDEV_LIBS) $(DLOPEN_LIBS) $(LIBDRM_LIB) EGL_CFLAGS = -D_EGL_MAIN=_eglBuiltInDriverDRI2 EGL_BUILTIN = true @@ -24,6 +23,12 @@ ifeq ($(SHARED_GLAPI),1) EGL_CFLAGS += -DHAVE_SHARED_GLAPI endif +ifneq ($(findstring x11, $(EGL_PLATFORMS)),) +EGL_SOURCES += platform_x11.c +EGL_INCLUDES += -DHAVE_X11_PLATFORM $(XCB_DRI2_CFLAGS) +EGL_LIBS += $(XCB_DRI2_LIBS) +endif + ifneq ($(findstring wayland, $(EGL_PLATFORMS)),) EGL_SOURCES += platform_wayland.c EGL_INCLUDES += -DHAVE_WAYLAND_PLATFORM $(WAYLAND_CFLAGS) \ diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c index afab679bff6..ea8c8fba8c0 100644 --- a/src/egl/drivers/dri2/egl_dri2.c +++ b/src/egl/drivers/dri2/egl_dri2.c @@ -200,13 +200,10 @@ dri2_add_config(_EGLDisplay *disp, const __DRIconfig *dri_config, int id, else if (!double_buffer && !conf->dri_single_config) conf->dri_single_config = dri_config; else - /* a similar config type is already added - * => attach it as new config - */ - num_configs = 0; + /* a similar config type is already added (unlikely) => discard */ + return NULL; } - - if (num_configs == 0) { + else if (num_configs == 0) { conf = malloc(sizeof *conf); if (conf == NULL) return NULL; @@ -224,6 +221,10 @@ dri2_add_config(_EGLDisplay *disp, const __DRIconfig *dri_config, int id, _eglLinkConfig(&conf->base); } + else { + assert(0); + return NULL; + } conf->base.SurfaceType |= surface_type & (!double_buffer ? EGL_PIXMAP_BIT: (EGL_WINDOW_BIT | EGL_PBUFFER_BIT | EGL_SWAP_BEHAVIOR_PRESERVED_BIT)); @@ -487,10 +488,12 @@ dri2_initialize(_EGLDriver *drv, _EGLDisplay *disp) return EGL_FALSE; switch (disp->Platform) { +#ifdef HAVE_X11_PLATFORM case _EGL_PLATFORM_X11: if (disp->Options.TestOnly) return EGL_TRUE; return dri2_initialize_x11(drv, disp); +#endif #ifdef HAVE_LIBUDEV case _EGL_PLATFORM_DRM: @@ -525,8 +528,10 @@ dri2_terminate(_EGLDriver *drv, _EGLDisplay *disp) if (dri2_dpy->fd) close(dri2_dpy->fd); dlclose(dri2_dpy->driver); +#ifdef HAVE_X11_PLATFORM if (disp->PlatformDisplay == NULL) xcb_disconnect(dri2_dpy->conn); +#endif free(dri2_dpy); disp->DriverData = NULL; @@ -835,7 +840,7 @@ dri2_create_image_khr_renderbuffer(_EGLDisplay *disp, _EGLContext *ctx, struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp); struct dri2_egl_context *dri2_ctx = dri2_egl_context(ctx); struct dri2_egl_image *dri2_img; - GLuint renderbuffer = (GLuint) buffer; + GLuint renderbuffer = (GLuint) (uintptr_t) buffer; if (renderbuffer == 0) { _eglError(EGL_BAD_PARAMETER, "dri2_create_image_khr"); @@ -870,7 +875,7 @@ dri2_create_image_mesa_drm_buffer(_EGLDisplay *disp, _EGLContext *ctx, (void) ctx; - name = (EGLint) buffer; + name = (EGLint) (uintptr_t) buffer; err = _eglParseImageAttribList(&attrs, disp, attr_list); if (err != EGL_SUCCESS) @@ -922,6 +927,7 @@ dri2_create_image_mesa_drm_buffer(_EGLDisplay *disp, _EGLContext *ctx, return &dri2_img->base; } +#ifdef HAVE_WAYLAND_PLATFORM static _EGLImage * dri2_reference_drm_image(_EGLDisplay *disp, _EGLContext *ctx, __DRIimage *dri_image, EGLint width, EGLint height) @@ -948,7 +954,6 @@ dri2_reference_drm_image(_EGLDisplay *disp, _EGLContext *ctx, attr_list); } -#ifdef HAVE_WAYLAND_PLATFORM static _EGLImage * dri2_create_image_wayland_wl_buffer(_EGLDisplay *disp, _EGLContext *ctx, EGLClientBuffer _buffer, diff --git a/src/egl/drivers/dri2/egl_dri2.h b/src/egl/drivers/dri2/egl_dri2.h index 99f990ac688..efcb366568e 100644 --- a/src/egl/drivers/dri2/egl_dri2.h +++ b/src/egl/drivers/dri2/egl_dri2.h @@ -28,10 +28,12 @@ #ifndef EGL_DRI2_INCLUDED #define EGL_DRI2_INCLUDED +#ifdef HAVE_X11_PLATFORM #include <xcb/xcb.h> #include <xcb/dri2.h> #include <xcb/xfixes.h> #include <X11/Xlib-xcb.h> +#endif #ifdef HAVE_WAYLAND_PLATFORM #include <wayland-client.h> @@ -64,7 +66,6 @@ struct dri2_egl_driver struct dri2_egl_display { - xcb_connection_t *conn; int dri2_major; int dri2_minor; __DRIscreen *dri_screen; @@ -84,6 +85,11 @@ struct dri2_egl_display __DRIdri2LoaderExtension dri2_loader_extension; __DRIswrastLoaderExtension swrast_loader_extension; const __DRIextension *extensions[3]; + +#ifdef HAVE_X11_PLATFORM + xcb_connection_t *conn; +#endif + #ifdef HAVE_WAYLAND_PLATFORM struct wl_display *wl_dpy; struct wl_drm *wl_server_drm; @@ -120,17 +126,19 @@ struct dri2_egl_surface { _EGLSurface base; __DRIdrawable *dri_drawable; - xcb_drawable_t drawable; __DRIbuffer buffers[5]; int buffer_count; - xcb_xfixes_region_t region; int have_fake_front; int swap_interval; +#ifdef HAVE_X11_PLATFORM + xcb_drawable_t drawable; + xcb_xfixes_region_t region; int depth; int bytes_per_pixel; xcb_gcontext_t gc; xcb_gcontext_t swapgc; +#endif enum dri2_surface_type type; #ifdef HAVE_WAYLAND_PLATFORM diff --git a/src/egl/drivers/dri2/platform_drm.c b/src/egl/drivers/dri2/platform_drm.c index 68912e36732..9811b280299 100644 --- a/src/egl/drivers/dri2/platform_drm.c +++ b/src/egl/drivers/dri2/platform_drm.c @@ -581,7 +581,8 @@ dri2_get_device_name(int fd) struct udev *udev; struct udev_device *device; struct stat buf; - char *device_name; + const char *const_device_name; + char *device_name = NULL; udev = udev_new(); if (fstat(fd, &buf) < 0) { @@ -596,10 +597,11 @@ dri2_get_device_name(int fd) goto out; } - device_name = udev_device_get_devnode(device); - if (!device_name) - goto out; - device_name = strdup(device_name); + const_device_name = udev_device_get_devnode(device); + if (!const_device_name) { + goto out; + } + device_name = strdup(const_device_name); out: udev_device_unref(device); @@ -690,7 +692,7 @@ dri2_initialize_drm(_EGLDriver *drv, _EGLDisplay *disp) memset(dri2_dpy, 0, sizeof *dri2_dpy); disp->DriverData = (void *) dri2_dpy; - dri2_dpy->fd = (int) disp->PlatformDisplay; + dri2_dpy->fd = (int) (intptr_t) disp->PlatformDisplay; dri2_dpy->driver_name = dri2_get_driver_for_fd(dri2_dpy->fd); if (dri2_dpy->driver_name == NULL) diff --git a/src/egl/drivers/dri2/platform_x11.c b/src/egl/drivers/dri2/platform_x11.c index 5d4ac6ae948..2e26ff00b67 100644 --- a/src/egl/drivers/dri2/platform_x11.c +++ b/src/egl/drivers/dri2/platform_x11.c @@ -784,7 +784,7 @@ dri2_create_image_khr_pixmap(_EGLDisplay *disp, _EGLContext *ctx, (void) ctx; - drawable = (xcb_drawable_t) buffer; + drawable = (xcb_drawable_t) (uintptr_t) buffer; xcb_dri2_create_drawable (dri2_dpy->conn, drawable); attachments[0] = XCB_DRI2_ATTACHMENT_BUFFER_FRONT_LEFT; buffers_cookie = diff --git a/src/egl/main/Makefile b/src/egl/main/Makefile index 820788d696b..cb8f0551293 100644 --- a/src/egl/main/Makefile +++ b/src/egl/main/Makefile @@ -58,11 +58,15 @@ LOCAL_LIBS = ifeq ($(filter dri2, $(EGL_DRIVERS_DIRS)),dri2) LOCAL_CFLAGS += -D_EGL_BUILT_IN_DRIVER_DRI2 LOCAL_LIBS += $(TOP)/src/egl/drivers/dri2/libegl_dri2.a +ifneq ($(findstring x11, $(EGL_PLATFORMS)),) +EGL_LIB_DEPS += $(XCB_DRI2_LIBS) +endif ifneq ($(findstring wayland, $(EGL_PLATFORMS)),) LOCAL_LIBS += $(TOP)/src/egl/wayland/wayland-drm/libwayland-drm.a endif -EGL_LIB_DEPS += $(XCB_DRI2_LIBS) $(LIBUDEV_LIBS) $(DLOPEN_LIBS) $(LIBDRM_LIB) $(WAYLAND_LIBS) +EGL_LIB_DEPS += $(LIBUDEV_LIBS) $(DLOPEN_LIBS) $(LIBDRM_LIB) $(WAYLAND_LIBS) endif + ifeq ($(filter glx, $(EGL_DRIVERS_DIRS)),glx) LOCAL_CFLAGS += -D_EGL_BUILT_IN_DRIVER_GLX LOCAL_LIBS += $(TOP)/src/egl/drivers/glx/libegl_glx.a diff --git a/src/egl/main/eglapi.c b/src/egl/main/eglapi.c index 336ec23da5a..bdfdcb3817d 100644 --- a/src/egl/main/eglapi.c +++ b/src/egl/main/eglapi.c @@ -1168,7 +1168,7 @@ eglQueryModeStringMESA(EGLDisplay dpy, EGLModeMESA mode) EGLDisplay EGLAPIENTRY eglGetDRMDisplayMESA(int fd) { - _EGLDisplay *dpy = _eglFindDisplay(_EGL_PLATFORM_DRM, (void *) fd); + _EGLDisplay *dpy = _eglFindDisplay(_EGL_PLATFORM_DRM, (void *) (intptr_t) fd); return _eglGetDisplayHandle(dpy); } diff --git a/src/gallium/auxiliary/gallivm/lp_bld_sample.c b/src/gallium/auxiliary/gallivm/lp_bld_sample.c index 4636371a0f5..cb6717d7f63 100644 --- a/src/gallium/auxiliary/gallivm/lp_bld_sample.c +++ b/src/gallium/auxiliary/gallivm/lp_bld_sample.c @@ -1055,7 +1055,7 @@ lp_build_sample_partial_offset(struct lp_build_context *bld, subcoord = LLVMBuildURem(builder, coord, block_width, ""); coord = LLVMBuildUDiv(builder, coord, block_width, ""); #else - unsigned logbase2 = util_unsigned_logbase2(block_length); + unsigned logbase2 = util_logbase2(block_length); LLVMValueRef block_shift = lp_build_const_int_vec(bld->gallivm, bld->type, logbase2); LLVMValueRef block_mask = lp_build_const_int_vec(bld->gallivm, bld->type, block_length - 1); subcoord = LLVMBuildAnd(builder, coord, block_mask, ""); diff --git a/src/gallium/auxiliary/util/u_math.h b/src/gallium/auxiliary/util/u_math.h index dad6a101fd7..2ecade5f7e4 100644 --- a/src/gallium/auxiliary/util/u_math.h +++ b/src/gallium/auxiliary/util/u_math.h @@ -413,22 +413,6 @@ unsigned ffs( unsigned u ) #define ffs __builtin_ffs #endif -#ifdef __MINGW32__ -#define ffs __builtin_ffs -#endif - - -/* Could also binary search for the highest bit. - */ -static INLINE unsigned -util_unsigned_logbase2(unsigned n) -{ - unsigned log2 = 0; - while (n >>= 1) - ++log2; - return log2; -} - /** * Return float bits. diff --git a/src/gallium/auxiliary/util/u_vbuf_mgr.c b/src/gallium/auxiliary/util/u_vbuf_mgr.c index dea2928f950..a034483ee5c 100644 --- a/src/gallium/auxiliary/util/u_vbuf_mgr.c +++ b/src/gallium/auxiliary/util/u_vbuf_mgr.c @@ -53,9 +53,11 @@ struct u_vbuf_mgr_elements { unsigned count; struct pipe_vertex_element ve[PIPE_MAX_ATTRIBS]; - /* If (velem[i].src_format != real_format[i]), the vertex buffer + unsigned src_format_size[PIPE_MAX_ATTRIBS]; + + /* If (velem[i].src_format != native_format[i]), the vertex buffer * referenced by the vertex element cannot be used for rendering and - * its vertex data must be translated to real_format[i]. */ + * its vertex data must be translated to native_format[i]. */ enum pipe_format native_format[PIPE_MAX_ATTRIBS]; unsigned native_format_size[PIPE_MAX_ATTRIBS]; @@ -353,6 +355,8 @@ u_vbuf_mgr_create_vertex_elements(struct u_vbuf_mgr *mgrb, for (i = 0; i < count; i++) { enum pipe_format format = ve->ve[i].src_format; + ve->src_format_size[i] = util_format_get_blocksize(format); + /* Choose a native format. * For now we don't care about the alignment, that's going to * be sorted out later. */ @@ -460,7 +464,6 @@ void u_vbuf_mgr_set_vertex_buffers(struct u_vbuf_mgr *mgrb, struct u_vbuf_mgr_priv *mgr = (struct u_vbuf_mgr_priv*)mgrb; unsigned i; - mgr->b.max_index = ~0; mgr->any_user_vbs = FALSE; mgr->incompatible_vb_layout = FALSE; @@ -483,23 +486,16 @@ void u_vbuf_mgr_set_vertex_buffers(struct u_vbuf_mgr *mgrb, pipe_resource_reference(&mgr->b.vertex_buffer[i].buffer, vb->buffer); pipe_resource_reference(&mgr->b.real_vertex_buffer[i], NULL); - if (u_vbuf_resource(vb->buffer)->user_ptr) { - mgr->any_user_vbs = TRUE; + if (!vb->buffer) { continue; } - pipe_resource_reference(&mgr->b.real_vertex_buffer[i], vb->buffer); - - /* The stride of zero means we will be fetching only the first - * vertex, so don't care about max_index. */ - if (!vb->stride) { + if (u_vbuf_resource(vb->buffer)->user_ptr) { + mgr->any_user_vbs = TRUE; continue; } - /* Update the maximum index. */ - mgr->b.max_index = - MIN2(mgr->b.max_index, - (vb->buffer->width0 - vb->buffer_offset) / vb->stride - 1); + pipe_resource_reference(&mgr->b.real_vertex_buffer[i], vb->buffer); } for (; i < mgr->b.nr_real_vertex_buffers; i++) { @@ -519,7 +515,7 @@ static void u_vbuf_upload_buffers(struct u_vbuf_mgr_priv *mgr, unsigned instance_count, boolean *upload_flushed) { - int i, nr = mgr->ve->count; + unsigned i, nr = mgr->ve->count; unsigned count = max_index + 1 - min_index; boolean uploaded[PIPE_MAX_ATTRIBS] = {0}; @@ -562,6 +558,40 @@ static void u_vbuf_upload_buffers(struct u_vbuf_mgr_priv *mgr, } } +static void u_vbuf_mgr_compute_max_index(struct u_vbuf_mgr_priv *mgr) +{ + unsigned i, nr = mgr->ve->count; + + mgr->b.max_index = ~0; + + for (i = 0; i < nr; i++) { + struct pipe_vertex_buffer *vb = + &mgr->b.vertex_buffer[mgr->ve->ve[i].vertex_buffer_index]; + int unused; + unsigned max_index; + + if (!vb->buffer || + !vb->stride || + u_vbuf_resource(vb->buffer)->user_ptr) { + continue; + } + + /* How many bytes is unused after the last vertex. + * width0 may be "count*stride - unused" and we have to compensate + * for that when dividing by stride. */ + unused = vb->stride - + (mgr->ve->ve[i].src_offset + mgr->ve->src_format_size[i]); + assert(unused >= 0); + + /* Compute the maximum index for this vertex element. */ + max_index = + (vb->buffer->width0 - vb->buffer_offset + (unsigned)unused) / + vb->stride - 1; + + mgr->b.max_index = MIN2(mgr->b.max_index, max_index); + } +} + void u_vbuf_mgr_draw_begin(struct u_vbuf_mgr *mgrb, const struct pipe_draw_info *info, boolean *buffers_updated, @@ -571,6 +601,8 @@ void u_vbuf_mgr_draw_begin(struct u_vbuf_mgr *mgrb, boolean bufs_updated = FALSE, upload_flushed = FALSE; int min_index, max_index; + u_vbuf_mgr_compute_max_index(mgr); + min_index = info->min_index - info->index_bias; if (info->max_index == ~0) { max_index = mgr->b.max_index; diff --git a/src/gallium/drivers/cell/spu/spu_vertex_shader.c b/src/gallium/drivers/cell/spu/spu_vertex_shader.c index 3e9804bf8ee..d6febd36f41 100644 --- a/src/gallium/drivers/cell/spu/spu_vertex_shader.c +++ b/src/gallium/drivers/cell/spu/spu_vertex_shader.c @@ -188,7 +188,7 @@ run_vertex_program(struct spu_vs_context *draw, PIPE_ALIGN_VAR(16) unsigned char -immediates[(sizeof(float) * 4 * TGSI_EXEC_NUM_IMMEDIATES) + 32]); +immediates[(sizeof(float) * 4 * TGSI_EXEC_NUM_IMMEDIATES) + 32]; void diff --git a/src/gallium/drivers/i915/i915_screen.c b/src/gallium/drivers/i915/i915_screen.c index 0e427749636..da96b420f2c 100644 --- a/src/gallium/drivers/i915/i915_screen.c +++ b/src/gallium/drivers/i915/i915_screen.c @@ -167,7 +167,7 @@ i915_get_param(struct pipe_screen *screen, enum pipe_cap cap) return 0; default: - debug_printf("%s: Unkown cap %u.\n", __FUNCTION__, cap); + debug_printf("%s: Unknown cap %u.\n", __FUNCTION__, cap); return 0; } } @@ -218,7 +218,7 @@ i915_get_shader_param(struct pipe_screen *screen, unsigned shader, enum pipe_sha case PIPE_SHADER_CAP_SUBROUTINES: return 0; default: - debug_printf("%s: Unkown cap %u.\n", __FUNCTION__, cap); + debug_printf("%s: Unknown cap %u.\n", __FUNCTION__, cap); return 0; } } @@ -244,7 +244,7 @@ i915_get_paramf(struct pipe_screen *screen, enum pipe_cap cap) return 16.0; default: - debug_printf("%s: Unkown cap %u.\n", __FUNCTION__, cap); + debug_printf("%s: Unknown cap %u.\n", __FUNCTION__, cap); return 0; } } diff --git a/src/gallium/drivers/llvmpipe/lp_rast_debug.c b/src/gallium/drivers/llvmpipe/lp_rast_debug.c index 64ac616f629..03e67dc8177 100644 --- a/src/gallium/drivers/llvmpipe/lp_rast_debug.c +++ b/src/gallium/drivers/llvmpipe/lp_rast_debug.c @@ -397,8 +397,8 @@ lp_debug_draw_bins_by_cmd_length( struct lp_scene *scene ) for (y = 0; y < scene->tiles_y; y++) { for (x = 0; x < scene->tiles_x; x++) { const char *bits = " ...,-~:;=o+xaw*#XAWWWWWWWWWWWWWWWW"; - int sz = lp_scene_bin_size(scene, x, y); - int sz2 = util_unsigned_logbase2(sz); + unsigned sz = lp_scene_bin_size(scene, x, y); + unsigned sz2 = util_logbase2(sz); debug_printf("%c", bits[MIN2(sz2,32)]); } debug_printf("\n"); diff --git a/src/gallium/drivers/nv50/nv50_screen.c b/src/gallium/drivers/nv50/nv50_screen.c index 4dad8599870..cc921d08666 100644 --- a/src/gallium/drivers/nv50/nv50_screen.c +++ b/src/gallium/drivers/nv50/nv50_screen.c @@ -89,6 +89,7 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_TEXTURE_SHADOW_MAP: case PIPE_CAP_NPOT_TEXTURES: case PIPE_CAP_ANISOTROPIC_FILTER: + return 1; case PIPE_CAP_SEAMLESS_CUBE_MAP: return nv50_screen(pscreen)->tesla->grclass >= NVA0_3D; case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: @@ -488,7 +489,7 @@ nv50_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev) BEGIN_RING(chan, RING_3D(LOCAL_ADDRESS_HIGH), 3); OUT_RELOCh(chan, screen->tls_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR); OUT_RELOCl(chan, screen->tls_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR); - OUT_RING (chan, util_unsigned_logbase2(tls_space / 8)); + OUT_RING (chan, util_logbase2(tls_space / 8)); ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, &screen->uniforms); diff --git a/src/gallium/drivers/nv50/nv50_transfer.c b/src/gallium/drivers/nv50/nv50_transfer.c index 74869774595..d9fb22aa673 100644 --- a/src/gallium/drivers/nv50/nv50_transfer.c +++ b/src/gallium/drivers/nv50/nv50_transfer.c @@ -209,6 +209,9 @@ nv50_miptree_transfer_new(struct pipe_context *pctx, uint32_t w, h, d, z, layer; int ret; + if (usage & PIPE_TRANSFER_MAP_DIRECTLY) + return NULL; + if (mt->layout_3d) { z = box->z; d = u_minify(res->depth0, level); diff --git a/src/gallium/drivers/nvc0/nvc0_pc_optimize.c b/src/gallium/drivers/nvc0/nvc0_pc_optimize.c index 7f5fbaff690..82a8397238d 100644 --- a/src/gallium/drivers/nvc0/nvc0_pc_optimize.c +++ b/src/gallium/drivers/nvc0/nvc0_pc_optimize.c @@ -1293,31 +1293,45 @@ nv_pass_cse(struct nv_pass *ctx, struct nv_basic_block *b) * neighbouring registers. CSE might have messed this up. * Just generate a MOV for each source to avoid conflicts if they're used in * multiple NV_OP_BIND at different positions. + * + * Add a dummy use of the pointer source of >= 8 byte loads after the load + * to prevent it from being assigned a register which overlaps the load's + * destination, which would produce random corruptions. */ static int -nv_pass_fix_bind(struct nv_pass *ctx, struct nv_basic_block *b) +nv_pass_fixups(struct nv_pass *ctx, struct nv_basic_block *b) { struct nv_value *val; - struct nv_instruction *bnd, *nvi, *next; + struct nv_instruction *fix, *nvi, *next; int s; - for (bnd = b->entry; bnd; bnd = next) { - next = bnd->next; - if (bnd->opcode != NV_OP_BIND) + for (fix = b->entry; fix; fix = next) { + next = fix->next; + + if (fix->opcode == NV_OP_LD) { + if (fix->indirect >= 0 && fix->src[0]->value->reg.size >= 8) { + nvi = nv_alloc_instruction(ctx->pc, NV_OP_UNDEF); + nv_reference(ctx->pc, nvi, 0, fix->src[fix->indirect]->value); + + nvc0_insn_insert_after(fix, nvi); + } continue; - for (s = 0; s < 4 && bnd->src[s]; ++s) { - val = bnd->src[s]->value; + } else + if (fix->opcode == NV_OP_BIND) { + for (s = 0; s < 4 && fix->src[s]; ++s) { + val = fix->src[s]->value; - nvi = nv_alloc_instruction(ctx->pc, NV_OP_MOV); - nvi->def[0] = new_value_like(ctx->pc, val); - nvi->def[0]->insn = nvi; - nv_reference(ctx->pc, nvi, 0, val); - nv_reference(ctx->pc, bnd, s, nvi->def[0]); + nvi = nv_alloc_instruction(ctx->pc, NV_OP_MOV); + nvi->def[0] = new_value_like(ctx->pc, val); + nvi->def[0]->insn = nvi; + nv_reference(ctx->pc, nvi, 0, val); + nv_reference(ctx->pc, fix, s, nvi->def[0]); - nvc0_insn_insert_before(bnd, nvi); + nvc0_insn_insert_before(fix, nvi); + } } } - DESCEND_ARBITRARY(s, nv_pass_fix_bind); + DESCEND_ARBITRARY(s, nv_pass_fixups); return 0; } @@ -1403,7 +1417,7 @@ nv_pc_pass0(struct nv_pc *pc, struct nv_basic_block *root) return ret; pc->pass_seq++; - ret = nv_pass_fix_bind(&pass, root); + ret = nv_pass_fixups(&pass, root); return ret; } diff --git a/src/gallium/drivers/nvc0/nvc0_transfer.c b/src/gallium/drivers/nvc0/nvc0_transfer.c index 7bbfe057e58..0509113e005 100644 --- a/src/gallium/drivers/nvc0/nvc0_transfer.c +++ b/src/gallium/drivers/nvc0/nvc0_transfer.c @@ -246,6 +246,9 @@ nvc0_miptree_transfer_new(struct pipe_context *pctx, uint32_t w, h, d, z, layer; int ret; + if (usage & PIPE_TRANSFER_MAP_DIRECTLY) + return NULL; + tx = CALLOC_STRUCT(nvc0_transfer); if (!tx) return NULL; diff --git a/src/gallium/drivers/nvfx/nvfx_screen.c b/src/gallium/drivers/nvfx/nvfx_screen.c index 4a97dfb9c25..78212029534 100644 --- a/src/gallium/drivers/nvfx/nvfx_screen.c +++ b/src/gallium/drivers/nvfx/nvfx_screen.c @@ -81,6 +81,12 @@ nvfx_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) return 0; // TODO: implement depth clamp case PIPE_CAP_PRIMITIVE_RESTART: return 0; // TODO: implement primitive restart + case PIPE_CAP_ARRAY_TEXTURES: + case PIPE_CAP_TGSI_INSTANCEID: + case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: + case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL: + case PIPE_CAP_SEAMLESS_CUBE_MAP: + case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: case PIPE_CAP_SHADER_STENCIL_EXPORT: return 0; case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: diff --git a/src/gallium/drivers/r300/r300_blit.c b/src/gallium/drivers/r300/r300_blit.c index 1217488bac7..4ec77df8fb7 100644 --- a/src/gallium/drivers/r300/r300_blit.c +++ b/src/gallium/drivers/r300/r300_blit.c @@ -113,7 +113,7 @@ static boolean r300_fast_zclear_allowed(struct r300_context *r300) struct pipe_framebuffer_state *fb = (struct pipe_framebuffer_state*)r300->fb_state.state; - return r300_resource(fb->zsbuf->texture)->tex.zmask_dwords[fb->zsbuf->u.tex.level]; + return r300_resource(fb->zsbuf->texture)->tex.zmask_dwords[fb->zsbuf->u.tex.level] != 0; } static boolean r300_hiz_clear_allowed(struct r300_context *r300) @@ -121,7 +121,7 @@ static boolean r300_hiz_clear_allowed(struct r300_context *r300) struct pipe_framebuffer_state *fb = (struct pipe_framebuffer_state*)r300->fb_state.state; - return r300_resource(fb->zsbuf->texture)->tex.hiz_dwords[fb->zsbuf->u.tex.level]; + return r300_resource(fb->zsbuf->texture)->tex.hiz_dwords[fb->zsbuf->u.tex.level] != 0; } static uint32_t r300_depth_clear_value(enum pipe_format format, @@ -206,23 +206,47 @@ static void r300_clear(struct pipe_context* pipe, (struct r300_hyperz_state*)r300->hyperz_state.state; uint32_t width = fb->width; uint32_t height = fb->height; - boolean can_hyperz = r300->rws->get_value(r300->rws, RADEON_VID_CAN_HYPERZ); uint32_t hyperz_dcv = hyperz->zb_depthclearvalue; /* Enable fast Z clear. * The zbuffer must be in micro-tiled mode, otherwise it locks up. */ - if ((buffers & PIPE_CLEAR_DEPTHSTENCIL) && can_hyperz) { - if (r300_fast_zclear_allowed(r300)) { - hyperz_dcv = hyperz->zb_depthclearvalue = - r300_depth_clear_value(fb->zsbuf->format, depth, stencil); - - r300_mark_atom_dirty(r300, &r300->zmask_clear); - buffers &= ~PIPE_CLEAR_DEPTHSTENCIL; - } - - if (r300_hiz_clear_allowed(r300)) { - r300->hiz_clear_value = r300_hiz_clear_value(depth); - r300_mark_atom_dirty(r300, &r300->hiz_clear); + if (buffers & PIPE_CLEAR_DEPTHSTENCIL) { + boolean zmask_clear, hiz_clear; + + zmask_clear = r300_fast_zclear_allowed(r300); + hiz_clear = r300_hiz_clear_allowed(r300); + + /* If we need Hyper-Z. */ + if (zmask_clear || hiz_clear) { + r300->num_z_clears++; + + /* Try to obtain the access to Hyper-Z buffers if we don't have one. */ + if (!r300->hyperz_enabled) { + r300->hyperz_enabled = + r300->rws->cs_request_feature(r300->cs, + RADEON_FID_HYPERZ_RAM_ACCESS, + TRUE); + if (r300->hyperz_enabled) { + /* Need to emit HyperZ buffer regs for the first time. */ + r300_mark_fb_state_dirty(r300, R300_CHANGED_HYPERZ_FLAG); + } + } + + /* Setup Hyper-Z clears. */ + if (r300->hyperz_enabled) { + if (zmask_clear) { + hyperz_dcv = hyperz->zb_depthclearvalue = + r300_depth_clear_value(fb->zsbuf->format, depth, stencil); + + r300_mark_atom_dirty(r300, &r300->zmask_clear); + buffers &= ~PIPE_CLEAR_DEPTHSTENCIL; + } + + if (hiz_clear) { + r300->hiz_clear_value = r300_hiz_clear_value(depth); + r300_mark_atom_dirty(r300, &r300->hiz_clear); + } + } } } @@ -323,7 +347,7 @@ static void r300_clear_depth_stencil(struct pipe_context *pipe, struct pipe_framebuffer_state *fb = (struct pipe_framebuffer_state*)r300->fb_state.state; - if (r300->zmask_in_use && !r300->hyperz_locked) { + if (r300->zmask_in_use && !r300->locked_zbuffer) { if (fb->zsbuf->texture == dst->texture) { r300_decompress_zmask(r300); } @@ -341,7 +365,7 @@ void r300_decompress_zmask(struct r300_context *r300) struct pipe_framebuffer_state *fb = (struct pipe_framebuffer_state*)r300->fb_state.state; - if (!r300->zmask_in_use || r300->hyperz_locked) + if (!r300->zmask_in_use || r300->locked_zbuffer) return; r300->zmask_decompress = TRUE; @@ -377,6 +401,8 @@ void r300_decompress_zmask_locked(struct r300_context *r300) r300_decompress_zmask_locked_unsafe(r300); r300->context.set_framebuffer_state(&r300->context, &saved_fb); util_unreference_framebuffer_state(&saved_fb); + + pipe_surface_reference(&r300->locked_zbuffer, NULL); } /* Copy a block of pixels from one surface to another using HW. */ @@ -423,7 +449,7 @@ static void r300_resource_copy_region(struct pipe_context *pipe, return; } - if (r300->zmask_in_use && !r300->hyperz_locked) { + if (r300->zmask_in_use && !r300->locked_zbuffer) { if (fb->zsbuf->texture == src || fb->zsbuf->texture == dst) { r300_decompress_zmask(r300); diff --git a/src/gallium/drivers/r300/r300_context.c b/src/gallium/drivers/r300/r300_context.c index 15d1278c3bb..0554c40eef0 100644 --- a/src/gallium/drivers/r300/r300_context.c +++ b/src/gallium/drivers/r300/r300_context.c @@ -26,6 +26,7 @@ #include "util/u_sampler.h" #include "util/u_simple_list.h" #include "util/u_upload_mgr.h" +#include "os/os_time.h" #include "r300_cb.h" #include "r300_context.h" @@ -95,6 +96,10 @@ static void r300_destroy_context(struct pipe_context* context) { struct r300_context* r300 = r300_context(context); + if (r300->cs && r300->hyperz_enabled) { + r300->rws->cs_request_feature(r300->cs, RADEON_FID_HYPERZ_RAM_ACCESS, FALSE); + } + if (r300->blitter) util_blitter_destroy(r300->blitter); if (r300->draw) @@ -167,8 +172,6 @@ static boolean r300_setup_atoms(struct r300_context* r300) boolean is_r500 = r300->screen->caps.is_r500; boolean has_tcl = r300->screen->caps.has_tcl; boolean drm_2_6_0 = r300->rws->get_value(r300->rws, RADEON_VID_DRM_2_6_0); - boolean can_hyperz = r300->rws->get_value(r300->rws, RADEON_VID_CAN_HYPERZ); - boolean has_hiz_ram = r300->screen->caps.hiz_ram > 0; /* Create the actual atom list. * @@ -219,13 +222,10 @@ static boolean r300_setup_atoms(struct r300_context* r300) /* TX. */ R300_INIT_ATOM(texture_cache_inval, 2); R300_INIT_ATOM(textures_state, 0); - if (can_hyperz) { - /* HiZ Clear */ - if (has_hiz_ram) - R300_INIT_ATOM(hiz_clear, 4); - /* zmask clear */ - R300_INIT_ATOM(zmask_clear, 4); - } + /* HiZ Clear */ + R300_INIT_ATOM(hiz_clear, r300->screen->caps.hiz_ram > 0 ? 4 : 0); + /* zmask clear */ + R300_INIT_ATOM(zmask_clear, r300->screen->caps.zmask_ram > 0 ? 4 : 0); /* ZB (unpipelined), SU. */ R300_INIT_ATOM(query_start, 4); @@ -503,6 +503,8 @@ struct pipe_context* r300_create_context(struct pipe_screen* screen, &dsa); } + r300->hyperz_time_of_last_flush = os_time_get(); + /* Print driver info. */ #ifdef DEBUG { @@ -512,7 +514,7 @@ struct pipe_context* r300_create_context(struct pipe_screen* screen, fprintf(stderr, "r300: DRM version: %d.%d.%d, Name: %s, ID: 0x%04x, GB: %d, Z: %d\n" "r300: GART size: %d MB, VRAM size: %d MB\n" - "r300: AA compression: %s, Z compression: %s, HiZ: %s\n", + "r300: AA compression RAM: %s, Z compression RAM: %s, HiZ RAM: %s\n", rws->get_value(rws, RADEON_VID_DRM_MAJOR), rws->get_value(rws, RADEON_VID_DRM_MINOR), rws->get_value(rws, RADEON_VID_DRM_PATCHLEVEL), @@ -522,10 +524,8 @@ struct pipe_context* r300_create_context(struct pipe_screen* screen, rws->get_value(rws, RADEON_VID_R300_Z_PIPES), rws->get_value(rws, RADEON_VID_GART_SIZE) >> 20, rws->get_value(rws, RADEON_VID_VRAM_SIZE) >> 20, - rws->get_value(rws, RADEON_VID_CAN_AACOMPRESS) ? "YES" : "NO", - rws->get_value(rws, RADEON_VID_CAN_HYPERZ) && + "YES", /* XXX really? */ r300->screen->caps.zmask_ram ? "YES" : "NO", - rws->get_value(rws, RADEON_VID_CAN_HYPERZ) && r300->screen->caps.hiz_ram ? "YES" : "NO"); } diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h index 8a0a54cf1e9..139dd210b8f 100644 --- a/src/gallium/drivers/r300/r300_context.h +++ b/src/gallium/drivers/r300/r300_context.h @@ -592,20 +592,6 @@ struct r300_context { boolean frag_clamp; /* Whether fast color clear is enabled. */ boolean cbzb_clear; - /* Whether ZMASK is enabled. */ - boolean zmask_in_use; - /* Whether ZMASK is being decompressed. */ - boolean zmask_decompress; - /* Whether ZMASK/HIZ is locked, i.e. should be disabled and cannot be taken over. */ - boolean hyperz_locked; - /* The zbuffer the ZMASK of which is locked. */ - struct pipe_surface *locked_zbuffer; - /* Whether HIZ is enabled. */ - boolean hiz_in_use; - /* HiZ function. Can be either MIN or MAX. */ - enum r300_hiz_func hiz_func; - /* HiZ clear value. */ - uint32_t hiz_clear_value; /* Whether fragment shader needs to be validated. */ enum r300_fs_validity_status fs_status; /* Framebuffer multi-write. */ @@ -629,6 +615,21 @@ struct r300_context { int vertex_arrays_offset; int vertex_arrays_instance_id; boolean instancing_enabled; + + /* Hyper-Z stats. */ + boolean hyperz_enabled; /* Whether it owns Hyper-Z access. */ + int64_t hyperz_time_of_last_flush; /* Time of the last flush with Z clear. */ + unsigned num_z_clears; /* Since the last flush. */ + + /* ZMask state. */ + boolean zmask_in_use; /* Whether ZMASK is enabled. */ + boolean zmask_decompress; /* Whether ZMASK is being decompressed. */ + struct pipe_surface *locked_zbuffer; /* Unbound zbuffer which still has data in ZMASK. */ + + /* HiZ state. */ + boolean hiz_in_use; /* Whether HIZ is enabled. */ + enum r300_hiz_func hiz_func; /* HiZ function. Can be either MIN or MAX. */ + uint32_t hiz_clear_value; /* HiZ clear value. */ }; #define foreach_atom(r300, atom) \ diff --git a/src/gallium/drivers/r300/r300_emit.c b/src/gallium/drivers/r300/r300_emit.c index 62435c5e2e2..874037ed9fd 100644 --- a/src/gallium/drivers/r300/r300_emit.c +++ b/src/gallium/drivers/r300/r300_emit.c @@ -375,7 +375,6 @@ void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state) struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state; struct r300_surface* surf; unsigned i; - boolean can_hyperz = r300->rws->get_value(r300->rws, RADEON_VID_CAN_HYPERZ); uint32_t rb3d_cctl = 0; CS_LOCALS(r300); @@ -432,7 +431,7 @@ void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state) OUT_CS_REG(R300_ZB_DEPTHPITCH, surf->pitch); OUT_CS_RELOC(surf); - if (can_hyperz) { + if (r300->hyperz_enabled) { /* HiZ RAM. */ OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0); OUT_CS_REG(R300_ZB_HIZ_PITCH, surf->pitch_hiz); diff --git a/src/gallium/drivers/r300/r300_flush.c b/src/gallium/drivers/r300/r300_flush.c index de7d77d608b..34f5419a864 100644 --- a/src/gallium/drivers/r300/r300_flush.c +++ b/src/gallium/drivers/r300/r300_flush.c @@ -27,17 +27,46 @@ #include "util/u_simple_list.h" #include "util/u_upload_mgr.h" +#include "os/os_time.h" + #include "r300_context.h" #include "r300_cs.h" #include "r300_emit.h" +static void r300_flush_and_cleanup(struct r300_context *r300, unsigned flags) +{ + struct r300_atom *atom; + + r300_emit_hyperz_end(r300); + r300_emit_query_end(r300); + if (r300->screen->caps.is_r500) + r500_emit_index_bias(r300, 0); + + r300->flush_counter++; + r300->rws->cs_flush(r300->cs, flags); + r300->dirty_hw = 0; + + /* New kitchen sink, baby. */ + foreach_atom(r300, atom) { + if (atom->state || atom->allow_null_state) { + r300_mark_atom_dirty(r300, atom); + } + } + r300->vertex_arrays_dirty = TRUE; + + /* Unmark HWTCL state for SWTCL. */ + if (!r300->screen->caps.has_tcl) { + r300->vs_state.dirty = FALSE; + r300->vs_constants.dirty = FALSE; + } +} + void r300_flush(struct pipe_context *pipe, unsigned flags, struct pipe_fence_handle **fence) { struct r300_context *r300 = r300_context(pipe); - struct r300_atom *atom; struct pb_buffer **rfence = (struct pb_buffer**)fence; if (r300->draw && !r300->draw_vbo_locked) @@ -56,32 +85,11 @@ void r300_flush(struct pipe_context *pipe, } if (r300->dirty_hw) { - r300_emit_hyperz_end(r300); - r300_emit_query_end(r300); - if (r300->screen->caps.is_r500) - r500_emit_index_bias(r300, 0); - - r300->flush_counter++; - r300->rws->cs_flush(r300->cs, flags); - r300->dirty_hw = 0; - - /* New kitchen sink, baby. */ - foreach_atom(r300, atom) { - if (atom->state || atom->allow_null_state) { - r300_mark_atom_dirty(r300, atom); - } - } - r300->vertex_arrays_dirty = TRUE; - - /* Unmark HWTCL state for SWTCL. */ - if (!r300->screen->caps.has_tcl) { - r300->vs_state.dirty = FALSE; - r300->vs_constants.dirty = FALSE; - } + r300_flush_and_cleanup(r300, flags); } else { if (rfence) { /* We have to create a fence object, but the command stream is empty - * and we cannot emit an empty CS. We must write some regs then. */ + * and we cannot emit an empty CS. Let's write to some reg. */ CS_LOCALS(r300); OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0); r300->rws->cs_flush(r300->cs, flags); @@ -91,6 +99,32 @@ void r300_flush(struct pipe_context *pipe, r300->rws->cs_flush(r300->cs, flags); } } + + /* Update Hyper-Z status. */ + if (r300->num_z_clears) { + r300->hyperz_time_of_last_flush = os_time_get(); + } else if (!r300->hyperz_time_of_last_flush > 2000000) { + /* 2 seconds without a Z clear pretty much means a dead context + * for HyperZ. */ + + r300->hiz_in_use = FALSE; + + /* Decompress Z buffer. */ + if (r300->zmask_in_use) { + if (r300->locked_zbuffer) { + r300_decompress_zmask_locked(r300); + } else { + r300_decompress_zmask(r300); + } + + r300_flush_and_cleanup(r300, flags); + } + + /* Release HyperZ. */ + r300->rws->cs_request_feature(r300->cs, RADEON_FID_HYPERZ_RAM_ACCESS, + FALSE); + } + r300->num_z_clears = 0; } static void r300_flush_wrapped(struct pipe_context *pipe, diff --git a/src/gallium/drivers/r300/r300_hyperz.c b/src/gallium/drivers/r300/r300_hyperz.c index ef330f34c9e..e946d61d0ed 100644 --- a/src/gallium/drivers/r300/r300_hyperz.c +++ b/src/gallium/drivers/r300/r300_hyperz.c @@ -43,16 +43,13 @@ static enum r300_hiz_func r300_get_hiz_func(struct r300_context *r300) { struct r300_dsa_state *dsa = r300->dsa_state.state; - if (!dsa->dsa.depth.enabled || !dsa->dsa.depth.writemask) - return HIZ_FUNC_NONE; - switch (dsa->dsa.depth.func) { case PIPE_FUNC_NEVER: case PIPE_FUNC_EQUAL: case PIPE_FUNC_NOTEQUAL: case PIPE_FUNC_ALWAYS: - return HIZ_FUNC_NONE; - + default: + /* Guess MAX for uncertain cases. */ case PIPE_FUNC_LESS: case PIPE_FUNC_LEQUAL: return HIZ_FUNC_MAX; @@ -60,10 +57,6 @@ static enum r300_hiz_func r300_get_hiz_func(struct r300_context *r300) case PIPE_FUNC_GREATER: case PIPE_FUNC_GEQUAL: return HIZ_FUNC_MIN; - - default: - assert(0); - return HIZ_FUNC_NONE; } } @@ -103,18 +96,21 @@ static boolean r300_dsa_stencil_op_not_keep(struct pipe_stencil_state *s) s->zfail_op != PIPE_STENCIL_OP_KEEP); } -static boolean r300_can_hiz(struct r300_context *r300) +static boolean r300_hiz_allowed(struct r300_context *r300) { struct r300_dsa_state *dsa = r300->dsa_state.state; struct r300_screen *r300screen = r300->screen; - /* shader writes depth - no HiZ */ - if (r300_fragment_shader_writes_depth(r300_fs(r300))) /* (5) */ + if (r300_fragment_shader_writes_depth(r300_fs(r300))) return FALSE; if (r300->query_current) return FALSE; + /* If the depth function is inverted, HiZ must be disabled. */ + if (!r300_is_hiz_func_valid(r300)) + return FALSE; + /* if stencil fail/zfail op is not KEEP */ if (r300_dsa_stencil_op_not_keep(&dsa->dsa.stencil[0]) || r300_dsa_stencil_op_not_keep(&dsa->dsa.stencil[1])) @@ -138,6 +134,7 @@ static void r300_update_hyperz(struct r300_context* r300) (struct r300_hyperz_state*)r300->hyperz_state.state; struct pipe_framebuffer_state *fb = (struct pipe_framebuffer_state*)r300->fb_state.state; + struct r300_dsa_state *dsa = r300->dsa_state.state; struct r300_resource *zstex = fb->zsbuf ? r300_resource(fb->zsbuf->texture) : NULL; @@ -151,55 +148,70 @@ static void r300_update_hyperz(struct r300_context* r300) return; } - if (!zstex || - !r300->rws->get_value(r300->rws, RADEON_VID_CAN_HYPERZ)) + if (!zstex || !r300->hyperz_enabled) return; - /* Zbuffer compression. */ - if (r300->zmask_in_use && !r300->hyperz_locked) { + /* Set the size of ZMASK tiles. */ + if (zstex->tex.zcomp8x8[fb->zsbuf->u.tex.level]) { + z->gb_z_peq_config |= R300_GB_Z_PEQ_CONFIG_Z_PEQ_SIZE_8_8; + } + + /* R500-specific features and optimizations. */ + if (r300->screen->caps.is_r500) { + z->zb_bw_cntl |= R500_PEQ_PACKING_ENABLE | + R500_COVERED_PTR_MASKING_ENABLE; + } + + /* Setup decompression if needed. No other HyperZ setting is required. */ + if (r300->zmask_decompress) { z->zb_bw_cntl |= R300_FAST_FILL_ENABLE | - /*R300_FORCE_COMPRESSED_STENCIL_VALUE_ENABLE |*/ R300_RD_COMP_ENABLE; + return; + } - if (!r300->zmask_decompress) { - z->zb_bw_cntl |= R300_WR_COMP_ENABLE; - } + /* Do not set anything if depth and stencil tests are off. */ + if (!dsa->dsa.depth.enabled && + !dsa->dsa.stencil[0].enabled && + !dsa->dsa.stencil[1].enabled) { + assert(!dsa->dsa.depth.writemask); + return; } - if (zstex->tex.zcomp8x8[fb->zsbuf->u.tex.level]) { - z->gb_z_peq_config |= R300_GB_Z_PEQ_CONFIG_Z_PEQ_SIZE_8_8; + /* Zbuffer compression. */ + if (r300->zmask_in_use && !r300->locked_zbuffer) { + z->zb_bw_cntl |= R300_FAST_FILL_ENABLE | + R300_RD_COMP_ENABLE | + R300_WR_COMP_ENABLE; } /* HiZ. */ - if (r300->hiz_in_use && !r300->hyperz_locked) { + if (r300->hiz_in_use && !r300->locked_zbuffer) { + /* HiZ cannot be used under some circumstances. */ + if (!r300_hiz_allowed(r300)) { + /* If writemask is disabled, the HiZ memory will not be changed, + * so we can keep its content for later. */ + if (dsa->dsa.depth.writemask) { + r300->hiz_in_use = FALSE; + } + return; + } + /* Set the HiZ function if needed. */ if (r300->hiz_func == HIZ_FUNC_NONE) { r300->hiz_func = r300_get_hiz_func(r300); } - /* If the depth function is inverted, HiZ must be disabled. */ - if (!r300_is_hiz_func_valid(r300)) { - r300->hiz_in_use = FALSE; - } else if (r300_can_hiz(r300)) { - /* Setup the HiZ bits. */ - z->zb_bw_cntl |= - R300_HIZ_ENABLE | + /* Setup the HiZ bits. */ + z->zb_bw_cntl |= R300_HIZ_ENABLE | (r300->hiz_func == HIZ_FUNC_MIN ? R300_HIZ_MIN : R300_HIZ_MAX); - z->sc_hyperz |= R300_SC_HYPERZ_ENABLE | - r300_get_sc_hz_max(r300); + z->sc_hyperz |= R300_SC_HYPERZ_ENABLE | + r300_get_sc_hz_max(r300); - if (r300->screen->caps.is_r500) { - z->zb_bw_cntl |= R500_HIZ_EQUAL_REJECT_ENABLE; - } + if (r300->screen->caps.is_r500) { + z->zb_bw_cntl |= R500_HIZ_EQUAL_REJECT_ENABLE; } } - - /* R500-specific features and optimizations. */ - if (r300->screen->caps.is_r500) { - z->zb_bw_cntl |= R500_PEQ_PACKING_ENABLE | - R500_COVERED_PTR_MASKING_ENABLE; - } } /*****************************************************************************/ diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c index 24b41d5085d..bc6c67dd034 100644 --- a/src/gallium/drivers/r300/r300_state.c +++ b/src/gallium/drivers/r300/r300_state.c @@ -768,7 +768,6 @@ void r300_mark_fb_state_dirty(struct r300_context *r300, enum r300_fb_state_change change) { struct pipe_framebuffer_state *state = r300->fb_state.state; - boolean can_hyperz = r300->rws->get_value(r300->rws, RADEON_VID_CAN_HYPERZ); r300_mark_atom_dirty(r300, &r300->gpu_flush); r300_mark_atom_dirty(r300, &r300->fb_state); @@ -797,7 +796,7 @@ void r300_mark_fb_state_dirty(struct r300_context *r300, r300->fb_state.size += 10; else if (state->zsbuf) { r300->fb_state.size += 10; - if (can_hyperz) + if (r300->hyperz_enabled) r300->fb_state.size += 8; } @@ -813,6 +812,7 @@ r300_set_framebuffer_state(struct pipe_context* pipe, struct pipe_framebuffer_state *old_state = r300->fb_state.state; unsigned max_width, max_height, i; uint32_t zbuffer_bpp = 0; + boolean unlock_zbuffer = FALSE; if (r300->screen->caps.is_r500) { max_width = max_height = 4096; @@ -828,7 +828,7 @@ r300_set_framebuffer_state(struct pipe_context* pipe, return; } - if (old_state->zsbuf && r300->zmask_in_use && !r300->hyperz_locked) { + if (old_state->zsbuf && r300->zmask_in_use && !r300->locked_zbuffer) { /* There is a zmask in use, what are we gonna do? */ if (state->zsbuf) { if (!pipe_surface_equal(old_state->zsbuf, state->zsbuf)) { @@ -838,10 +838,9 @@ r300_set_framebuffer_state(struct pipe_context* pipe, } } else { /* We don't bind another zbuffer, so lock the current one. */ - r300->hyperz_locked = TRUE; pipe_surface_reference(&r300->locked_zbuffer, old_state->zsbuf); } - } else if (r300->hyperz_locked && r300->locked_zbuffer) { + } else if (r300->locked_zbuffer) { /* We have a locked zbuffer now, what are we gonna do? */ if (state->zsbuf) { if (!pipe_surface_equal(r300->locked_zbuffer, state->zsbuf)) { @@ -851,11 +850,11 @@ r300_set_framebuffer_state(struct pipe_context* pipe, r300->hiz_in_use = FALSE; } else { /* We are binding the locked zbuffer again, so unlock it. */ - r300->hyperz_locked = FALSE; + unlock_zbuffer = TRUE; } } } - assert(state->zsbuf || r300->hyperz_locked || !r300->zmask_in_use); + assert(state->zsbuf || (r300->locked_zbuffer && !unlock_zbuffer) || !r300->zmask_in_use); /* Need to reset clamping or colormask. */ r300_mark_atom_dirty(r300, &r300->blend_state); @@ -870,7 +869,7 @@ r300_set_framebuffer_state(struct pipe_context* pipe, util_copy_framebuffer_state(r300->fb_state.state, state); - if (!r300->hyperz_locked) { + if (unlock_zbuffer) { pipe_surface_reference(&r300->locked_zbuffer, NULL); } diff --git a/src/gallium/drivers/r300/r300_state_derived.c b/src/gallium/drivers/r300/r300_state_derived.c index afc1451183d..04499c78cc6 100644 --- a/src/gallium/drivers/r300/r300_state_derived.c +++ b/src/gallium/drivers/r300/r300_state_derived.c @@ -965,7 +965,7 @@ static void r300_decompress_depth_textures(struct r300_context *r300) state->sampler_state_count); unsigned i; - if (!r300->hyperz_locked || !r300->locked_zbuffer) { + if (!r300->locked_zbuffer) { return; } diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index 502f2663e8b..654b04ea1bd 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -310,6 +310,7 @@ static void *evergreen_create_sampler_state(struct pipe_context *ctx, { struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); union util_color uc; + unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0; if (rstate == NULL) { return NULL; @@ -321,9 +322,10 @@ static void *evergreen_create_sampler_state(struct pipe_context *ctx, S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) | S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) | S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) | - S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) | - S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) | + S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) | + S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) | S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) | + S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) | S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) | S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL); r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0, @@ -429,7 +431,9 @@ static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_conte S_030014_LAST_LEVEL(state->u.tex.last_level) | S_030014_BASE_ARRAY(0) | S_030014_LAST_ARRAY(0), 0xffffffff, NULL); - r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6, 0x0, 0xFFFFFFFF, NULL); + r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6, + S_030018_MAX_ANISO(4 /* max 16 samples */), + 0xFFFFFFFF, NULL); r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7, S_03001C_DATA_FORMAT(format) | S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL); diff --git a/src/gallium/drivers/r600/evergreend.h b/src/gallium/drivers/r600/evergreend.h index 670606d9b07..3e878106bea 100644 --- a/src/gallium/drivers/r600/evergreend.h +++ b/src/gallium/drivers/r600/evergreend.h @@ -1027,6 +1027,9 @@ #define G_030014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF) #define C_030014_LAST_ARRAY 0xC001FFFF #define R_030018_SQ_TEX_RESOURCE_WORD6_0 0x030018 +#define S_030018_MAX_ANISO(x) (((x) & 0x7) << 0) +#define G_030018_MAX_ANISO(x) (((x) >> 0) & 0x7) +#define C_030018_MAX_ANISO 0xFFFFFFF8 #define S_030018_PERF_MODULATION(x) (((x) & 0x7) << 3) #define G_030018_PERF_MODULATION(x) (((x) >> 3) & 0x7) #define C_030018_PERF_MODULATION 0xFFFFFFC7 @@ -1141,6 +1144,9 @@ #define S_03C000_MIP_FILTER(x) (((x) & 0x3) << 15) #define G_03C000_MIP_FILTER(x) (((x) >> 15) & 0x3) #define C_03C000_MIP_FILTER 0xFFFE7FFF +#define S_03C000_MAX_ANISO(x) (((x) & 0x7) << 17) +#define G_03C000_MAX_ANISO(x) (((x) >> 17) & 0x7) +#define C_03C000_MAX_ANISO 0xFFF1FFFF #define S_03C000_BORDER_COLOR_TYPE(x) (((x) & 0x3) << 20) #define G_03C000_BORDER_COLOR_TYPE(x) (((x) >> 20) & 0x3) #define C_03C000_BORDER_COLOR_TYPE 0xFFCFFFFF diff --git a/src/gallium/drivers/r600/r600.h b/src/gallium/drivers/r600/r600.h index 33aa45088a8..7b57fc80dc2 100644 --- a/src/gallium/drivers/r600/r600.h +++ b/src/gallium/drivers/r600/r600.h @@ -193,8 +193,6 @@ struct r600_block { }; struct r600_range { - unsigned start_offset; - unsigned end_offset; struct r600_block **blocks; }; @@ -239,9 +237,7 @@ struct r600_query { struct r600_context { struct radeon *radeon; - unsigned hash_size; - unsigned hash_shift; - struct r600_range range[256]; + struct r600_range *range; unsigned nblocks; struct r600_block **blocks; struct list_head dirty; diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h index aa5ef4efb3b..0e4cfeb5b80 100644 --- a/src/gallium/drivers/r600/r600_pipe.h +++ b/src/gallium/drivers/r600/r600_pipe.h @@ -317,4 +317,13 @@ static INLINE u32 S_FIXED(float value, u32 frac_bits) } #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y)) +static inline unsigned r600_tex_aniso_filter(unsigned filter) +{ + if (filter <= 1) return 0; + if (filter <= 2) return 1; + if (filter <= 4) return 2; + if (filter <= 8) return 3; + /* else */ return 4; +} + #endif diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index b9084c953ee..8098e489d0f 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -374,6 +374,7 @@ static void *r600_create_sampler_state(struct pipe_context *ctx, { struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); union util_color uc; + unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0; if (rstate == NULL) { return NULL; @@ -385,9 +386,10 @@ static void *r600_create_sampler_state(struct pipe_context *ctx, S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) | S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) | S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) | - S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) | - S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) | + S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) | + S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) | S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) | + S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) | S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) | S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL); r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0, @@ -497,7 +499,8 @@ static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *c S_038014_BASE_ARRAY(state->u.tex.first_layer) | S_038014_LAST_ARRAY(state->u.tex.last_layer), 0xFFFFFFFF, NULL); r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6, - S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL); + S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) | + S_038018_MAX_ANISO(4 /* max 16 samples */), 0xFFFFFFFF, NULL); return &resource->base; } diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h index 8296b52eb94..9281b08bd82 100644 --- a/src/gallium/drivers/r600/r600d.h +++ b/src/gallium/drivers/r600/r600d.h @@ -1012,6 +1012,9 @@ #define S_038018_MPEG_CLAMP(x) (((x) & 0x3) << 0) #define G_038018_MPEG_CLAMP(x) (((x) >> 0) & 0x3) #define C_038018_MPEG_CLAMP 0xFFFFFFFC +#define S_038018_MAX_ANISO(x) (((x) & 0x7) << 2) +#define G_038018_MAX_ANISO(x) (((x) >> 2) & 0x7) +#define C_038018_MAX_ANISO 0xFFFFFFE3 #define S_038018_PERF_MODULATION(x) (((x) & 0x7) << 5) #define G_038018_PERF_MODULATION(x) (((x) >> 5) & 0x7) #define C_038018_PERF_MODULATION 0xFFFFFF1F @@ -1090,6 +1093,9 @@ #define S_03C000_MIP_FILTER(x) (((x) & 0x3) << 17) #define G_03C000_MIP_FILTER(x) (((x) >> 17) & 0x3) #define C_03C000_MIP_FILTER 0xFFF9FFFF +#define S_03C000_MAX_ANISO(x) (((x) & 0x7) << 19) +#define G_03C000_MAX_ANISO(x) (((x) >> 19) & 0x7) +#define C_03C000_MAX_ANISO 0xFFB7FFFF #define S_03C000_BORDER_COLOR_TYPE(x) (((x) & 0x3) << 22) #define G_03C000_BORDER_COLOR_TYPE(x) (((x) >> 22) & 0x3) #define C_03C000_BORDER_COLOR_TYPE 0xFF3FFFFF @@ -1152,6 +1158,9 @@ #define S_03C008_PERF_Z(x) (((x) & 0x3) << 18) #define G_03C008_PERF_Z(x) (((x) >> 18) & 0x3) #define C_03C008_PERF_Z 0xFFF3FFFF +#define S_03C008_ANISO_BIAS(x) (((x) & 0x3f) << 22) +#define G_03C008_ANISO_BIAS(x) (((x) >> 22) & 0x3f) +#define C_03C008_ANISO_BIAS (~(0x3f << 22)) #define S_03C008_FETCH_4(x) (((x) & 0x1) << 26) #define G_03C008_FETCH_4(x) (((x) >> 26) & 0x1) #define C_03C008_FETCH_4 0xFBFFFFFF diff --git a/src/gallium/drivers/softpipe/sp_tex_sample.c b/src/gallium/drivers/softpipe/sp_tex_sample.c index 02892c16bde..1446aee2aa4 100644 --- a/src/gallium/drivers/softpipe/sp_tex_sample.c +++ b/src/gallium/drivers/softpipe/sp_tex_sample.c @@ -2243,8 +2243,8 @@ sp_sampler_variant_bind_view( struct sp_sampler_variant *samp, samp->view = view; samp->cache = tex_cache; - samp->xpot = util_unsigned_logbase2( texture->width0 ); - samp->ypot = util_unsigned_logbase2( texture->height0 ); + samp->xpot = util_logbase2( texture->width0 ); + samp->ypot = util_logbase2( texture->height0 ); samp->level = view->u.tex.first_level; } diff --git a/src/gallium/include/pipe/p_config.h b/src/gallium/include/pipe/p_config.h index 74a1fa29781..1818c8b9e9a 100644 --- a/src/gallium/include/pipe/p_config.h +++ b/src/gallium/include/pipe/p_config.h @@ -111,14 +111,28 @@ * Endian detection. */ +#ifdef __GLIBC__ +#include <endian.h> + +#if __BYTE_ORDER == __LITTLE_ENDIAN +# define PIPE_ARCH_LITTLE_ENDIAN +#elif __BYTE_ORDER == __BIG_ENDIAN +# define PIPE_ARCH_BIG_ENDIAN +#endif + +#else + #if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64) #define PIPE_ARCH_LITTLE_ENDIAN #elif defined(PIPE_ARCH_PPC) || defined(PIPE_ARCH_PPC_64) #define PIPE_ARCH_BIG_ENDIAN -#else -#define PIPE_ARCH_UNKNOWN_ENDIAN #endif +#endif + +#if !defined(PIPE_ARCH_LITTLE_ENDIAN) && !defined(PIPE_ARCH_BIG_ENDIAN) +#error Unknown Endianness +#endif #if !defined(PIPE_OS_EMBEDDED) diff --git a/src/gallium/state_trackers/egl/Makefile b/src/gallium/state_trackers/egl/Makefile index 53673a78a94..763e7b58a49 100644 --- a/src/gallium/state_trackers/egl/Makefile +++ b/src/gallium/state_trackers/egl/Makefile @@ -6,6 +6,7 @@ common_INCLUDES = \ -I$(TOP)/src/gallium/include \ -I$(TOP)/src/gallium/auxiliary \ -I$(TOP)/src/egl/main \ + -I$(TOP)/src/egl/wayland/wayland-drm/ \ -I$(TOP)/include common_SOURCES = $(wildcard common/*.c) @@ -56,6 +57,7 @@ endif ifneq ($(findstring wayland, $(EGL_PLATFORMS)),) EGL_OBJECTS += $(wayland_OBJECTS) EGL_CPPFLAGS += -DHAVE_WAYLAND_BACKEND +DEFINES += -DHAVE_WAYLAND_BACKEND endif ifneq ($(findstring drm, $(EGL_PLATFORMS)),) EGL_OBJECTS += $(drm_OBJECTS) diff --git a/src/gallium/state_trackers/egl/common/egl_g3d.c b/src/gallium/state_trackers/egl/common/egl_g3d.c index 2c7f3bde4f0..4bd865638a3 100644 --- a/src/gallium/state_trackers/egl/common/egl_g3d.c +++ b/src/gallium/state_trackers/egl/common/egl_g3d.c @@ -552,6 +552,11 @@ egl_g3d_initialize(_EGLDriver *drv, _EGLDisplay *dpy) if (dpy->Platform == _EGL_PLATFORM_WAYLAND && gdpy->native->buffer) dpy->Extensions.MESA_drm_image = EGL_TRUE; +#ifdef EGL_WL_bind_wayland_display + if (gdpy->native->wayland_bufmgr) + dpy->Extensions.WL_bind_wayland_display = EGL_TRUE; +#endif + if (egl_g3d_add_configs(drv, dpy, 1) == 1) { _eglError(EGL_NOT_INITIALIZED, "eglInitialize(unable to add configs)"); goto fail; diff --git a/src/gallium/state_trackers/egl/common/egl_g3d_api.c b/src/gallium/state_trackers/egl/common/egl_g3d_api.c index f1568329ecf..8b1821e0055 100644 --- a/src/gallium/state_trackers/egl/common/egl_g3d_api.c +++ b/src/gallium/state_trackers/egl/common/egl_g3d_api.c @@ -868,6 +868,34 @@ egl_g3d_show_screen_surface(_EGLDriver *drv, _EGLDisplay *dpy, #endif /* EGL_MESA_screen_surface */ +#ifdef EGL_WL_bind_wayland_display + +static EGLBoolean +egl_g3d_bind_wayland_display_wl(_EGLDriver *drv, _EGLDisplay *dpy, + struct wl_display *wl_dpy) +{ + struct egl_g3d_display *gdpy = egl_g3d_display(dpy); + + if (!gdpy->native->wayland_bufmgr) + return EGL_FALSE; + + return gdpy->native->wayland_bufmgr->bind_display(gdpy->native, wl_dpy); +} + +static EGLBoolean +egl_g3d_unbind_wayland_display_wl(_EGLDriver *drv, _EGLDisplay *dpy, + struct wl_display *wl_dpy) +{ + struct egl_g3d_display *gdpy = egl_g3d_display(dpy); + + if (!gdpy->native->wayland_bufmgr) + return EGL_FALSE; + + return gdpy->native->wayland_bufmgr->unbind_display(gdpy->native, wl_dpy); +} + +#endif /* EGL_WL_bind_wayland_display */ + void egl_g3d_init_driver_api(_EGLDriver *drv) { @@ -897,6 +925,11 @@ egl_g3d_init_driver_api(_EGLDriver *drv) drv->API.CreateDRMImageMESA = egl_g3d_create_drm_image; drv->API.ExportDRMImageMESA = egl_g3d_export_drm_image; #endif +#ifdef EGL_WL_bind_wayland_display + drv->API.BindWaylandDisplayWL = egl_g3d_bind_wayland_display_wl; + drv->API.UnbindWaylandDisplayWL = egl_g3d_unbind_wayland_display_wl; + +#endif #ifdef EGL_KHR_reusable_sync drv->API.CreateSyncKHR = egl_g3d_create_sync; diff --git a/src/gallium/state_trackers/egl/common/egl_g3d_image.c b/src/gallium/state_trackers/egl/common/egl_g3d_image.c index e1c83168b3a..210b8c2ee82 100644 --- a/src/gallium/state_trackers/egl/common/egl_g3d_image.c +++ b/src/gallium/state_trackers/egl/common/egl_g3d_image.c @@ -179,6 +179,27 @@ egl_g3d_reference_drm_buffer(_EGLDisplay *dpy, EGLint name, #endif /* EGL_MESA_drm_image */ +#ifdef EGL_WL_bind_wayland_display + +static struct pipe_resource * +egl_g3d_reference_wl_buffer(_EGLDisplay *dpy, struct wl_buffer *buffer, + _EGLImage *img, const EGLint *attribs) +{ + struct egl_g3d_display *gdpy = egl_g3d_display(dpy); + struct pipe_resource *resource = NULL, *tmp = NULL; + + if (!gdpy->native->wayland_bufmgr) + return NULL; + + tmp = gdpy->native->wayland_bufmgr->buffer_get_resource(gdpy->native, buffer); + + pipe_resource_reference(&resource, tmp); + + return resource; +} + +#endif /* EGL_WL_bind_wayland_display */ + _EGLImage * egl_g3d_create_image(_EGLDriver *drv, _EGLDisplay *dpy, _EGLContext *ctx, EGLenum target, EGLClientBuffer buffer, @@ -210,6 +231,12 @@ egl_g3d_create_image(_EGLDriver *drv, _EGLDisplay *dpy, _EGLContext *ctx, (EGLint) buffer, &gimg->base, attribs); break; #endif +#ifdef EGL_WL_bind_wayland_display + case EGL_WAYLAND_BUFFER_WL: + ptex = egl_g3d_reference_wl_buffer(dpy, + (struct wl_buffer *) buffer, &gimg->base, attribs); + break; +#endif default: ptex = NULL; break; diff --git a/src/gallium/state_trackers/egl/common/native.h b/src/gallium/state_trackers/egl/common/native.h index 9246f8c32a4..8646e52ed7c 100644 --- a/src/gallium/state_trackers/egl/common/native.h +++ b/src/gallium/state_trackers/egl/common/native.h @@ -40,6 +40,7 @@ extern "C" { #include "native_buffer.h" #include "native_modeset.h" +#include "native_wayland_bufmgr.h" /** * Only color buffers are listed. The others are allocated privately through, @@ -198,6 +199,7 @@ struct native_display { const struct native_display_buffer *buffer; const struct native_display_modeset *modeset; + const struct native_display_wayland_bufmgr *wayland_bufmgr; }; /** diff --git a/src/gallium/state_trackers/egl/common/native_wayland_bufmgr.h b/src/gallium/state_trackers/egl/common/native_wayland_bufmgr.h new file mode 100644 index 00000000000..b29fd15c1ae --- /dev/null +++ b/src/gallium/state_trackers/egl/common/native_wayland_bufmgr.h @@ -0,0 +1,46 @@ +/* + * Mesa 3-D graphics library + * Version: 7.11 + * + * Copyright (C) 2011 Benjamin Franzke <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _NATIVE_WAYLAND_BUFMGR_H_ +#define _NATIVE_WAYLAND_BUFMGR_H_ + +struct native_display; +struct wl_display; +struct wl_buffer; +struct pipe_resource; + +struct native_display_wayland_bufmgr { + boolean (*bind_display)(struct native_display *ndpy, + struct wl_display *wl_dpy); + + boolean (*unbind_display)(struct native_display *ndpy, + struct wl_display *wl_dpy); + + struct pipe_resource *(*buffer_get_resource)(struct native_display *ndpy, + struct wl_buffer *buffer); + +}; + +#endif /* _NATIVE_WAYLAND_BUFMGR_H_ */ diff --git a/src/gallium/state_trackers/egl/common/native_wayland_drm_bufmgr_helper.c b/src/gallium/state_trackers/egl/common/native_wayland_drm_bufmgr_helper.c new file mode 100644 index 00000000000..bc2cee4c386 --- /dev/null +++ b/src/gallium/state_trackers/egl/common/native_wayland_drm_bufmgr_helper.c @@ -0,0 +1,57 @@ +#include <stdint.h> +#include <string.h> + +#include "native.h" +#include "util/u_inlines.h" +#include "state_tracker/drm_driver.h" + +#ifdef HAVE_WAYLAND_BACKEND + +#include <wayland-server.h> +#include <wayland-drm-server-protocol.h> + +#include "native_wayland_drm_bufmgr_helper.h" + +void * +egl_g3d_wl_drm_helper_reference_buffer(void *user_data, uint32_t name, + int32_t width, int32_t height, + uint32_t stride, + struct wl_visual *visual) +{ + struct native_display *ndpy = user_data; + struct pipe_resource templ; + struct winsys_handle wsh; + enum pipe_format format = PIPE_FORMAT_B8G8R8A8_UNORM; + + memset(&templ, 0, sizeof(templ)); + templ.target = PIPE_TEXTURE_2D; + templ.format = format; + templ.bind = PIPE_BIND_RENDER_TARGET | PIPE_BIND_SAMPLER_VIEW; + templ.width0 = width; + templ.height0 = height; + templ.depth0 = 1; + templ.array_size = 1; + + memset(&wsh, 0, sizeof(wsh)); + wsh.handle = name; + wsh.stride = stride; + + return ndpy->screen->resource_from_handle(ndpy->screen, &templ, &wsh); +} + +void +egl_g3d_wl_drm_helper_unreference_buffer(void *user_data, void *buffer) +{ + struct pipe_resource *resource = buffer; + + pipe_resource_reference(&resource, NULL); +} + +struct pipe_resource * +egl_g3d_wl_drm_common_wl_buffer_get_resource(struct native_display *ndpy, + struct wl_buffer *buffer) +{ + return wayland_drm_buffer_get_buffer(buffer); +} + +#endif diff --git a/src/gallium/state_trackers/egl/common/native_wayland_drm_bufmgr_helper.h b/src/gallium/state_trackers/egl/common/native_wayland_drm_bufmgr_helper.h new file mode 100644 index 00000000000..71cb6c52b26 --- /dev/null +++ b/src/gallium/state_trackers/egl/common/native_wayland_drm_bufmgr_helper.h @@ -0,0 +1,44 @@ +/* + * Mesa 3-D graphics library + * Version: 7.11 + * + * Copyright (C) 2011 Benjamin Franzke <[email protected]> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _NATIVE_WAYLAND_DRM_BUFMGR_HELPER_H_ +#define _NATIVE_WAYLAND_DRM_BUFMGR_HELPER_H_ + +#include "wayland-drm.h" + +void * +egl_g3d_wl_drm_helper_reference_buffer(void *user_data, uint32_t name, + int32_t width, int32_t height, + uint32_t stride, + struct wl_visual *visual); + +void +egl_g3d_wl_drm_helper_unreference_buffer(void *user_data, void *buffer); + +struct pipe_resource * +egl_g3d_wl_drm_common_wl_buffer_get_resource(struct native_display *ndpy, + struct wl_buffer *buffer); + +#endif /* _NATIVE_WAYLAND_DRM_BUFMGR_HELPER_H_ */ diff --git a/src/gallium/state_trackers/egl/drm/native_drm.c b/src/gallium/state_trackers/egl/drm/native_drm.c index 9863329ff40..c89a6d4767e 100644 --- a/src/gallium/state_trackers/egl/drm/native_drm.c +++ b/src/gallium/state_trackers/egl/drm/native_drm.c @@ -23,6 +23,7 @@ * DEALINGS IN THE SOFTWARE. */ +#include <string.h> #include <sys/types.h> #include <sys/stat.h> #include <fcntl.h> @@ -36,6 +37,10 @@ #include <radeon_drm.h> #include "radeon/drm/radeon_drm_public.h" +#ifdef HAVE_LIBUDEV +#include <libudev.h> +#endif + static boolean drm_display_is_format_supported(struct native_display *ndpy, enum pipe_format fmt, boolean is_color) @@ -126,6 +131,9 @@ drm_display_destroy(struct native_display *ndpy) ndpy_uninit(ndpy); + if (drmdpy->device_name) + FREE(drmdpy->device_name); + if (drmdpy->fd >= 0) close(drmdpy->fd); @@ -207,6 +215,101 @@ static struct native_display_buffer drm_display_buffer = { drm_display_export_buffer }; +static int +drm_display_authenticate(void *user_data, uint32_t magic) +{ + struct native_display *ndpy = user_data; + struct drm_display *drmdpy = drm_display(ndpy); + + return drmAuthMagic(drmdpy->fd, magic); +} + +static char * +drm_get_device_name(int fd) +{ + char *device_name = NULL; +#ifdef HAVE_LIBUDEV + struct udev *udev; + struct udev_device *device; + struct stat buf; + const char *tmp; + + udev = udev_new(); + if (fstat(fd, &buf) < 0) { + _eglLog(_EGL_WARNING, "failed to stat fd %d", fd); + goto out; + } + + device = udev_device_new_from_devnum(udev, 'c', buf.st_rdev); + if (device == NULL) { + _eglLog(_EGL_WARNING, + "could not create udev device for fd %d", fd); + goto out; + } + + tmp = udev_device_get_devnode(device); + if (!tmp) + goto out; + device_name = strdup(tmp); + +out: + udev_device_unref(device); + udev_unref(udev); + +#endif + return device_name; +} + +#ifdef HAVE_WAYLAND_BACKEND + +static struct wayland_drm_callbacks wl_drm_callbacks = { + drm_display_authenticate, + egl_g3d_wl_drm_helper_reference_buffer, + egl_g3d_wl_drm_helper_unreference_buffer +}; + +static boolean +drm_display_bind_wayland_display(struct native_display *ndpy, + struct wl_display *wl_dpy) +{ + struct drm_display *drmdpy = drm_display(ndpy); + + if (drmdpy->wl_server_drm) + return FALSE; + + drmdpy->wl_server_drm = wayland_drm_init(wl_dpy, + drmdpy->device_name, + &wl_drm_callbacks, ndpy); + + if (!drmdpy->wl_server_drm) + return FALSE; + + return TRUE; +} + +static boolean +drm_display_unbind_wayland_display(struct native_display *ndpy, + struct wl_display *wl_dpy) +{ + struct drm_display *drmdpy = drm_display(ndpy); + + if (!drmdpy->wl_server_drm) + return FALSE; + + wayland_drm_uninit(drmdpy->wl_server_drm); + drmdpy->wl_server_drm = NULL; + + return TRUE; +} + +static struct native_display_wayland_bufmgr drm_display_wayland_bufmgr = { + drm_display_bind_wayland_display, + drm_display_unbind_wayland_display, + egl_g3d_wl_drm_common_wl_buffer_get_resource +}; + +#endif /* HAVE_WAYLAND_BACKEND */ + static struct native_display * drm_create_display(int fd, struct native_event_handler *event_handler, void *user_data) @@ -218,6 +321,7 @@ drm_create_display(int fd, struct native_event_handler *event_handler, return NULL; drmdpy->fd = fd; + drmdpy->device_name = drm_get_device_name(fd); drmdpy->event_handler = event_handler; drmdpy->base.user_data = user_data; @@ -231,6 +335,10 @@ drm_create_display(int fd, struct native_event_handler *event_handler, drmdpy->base.get_configs = drm_display_get_configs; drmdpy->base.buffer = &drm_display_buffer; +#ifdef HAVE_WAYLAND_BACKEND + if (drmdpy->device_name) + drmdpy->base.wayland_bufmgr = &drm_display_wayland_bufmgr; +#endif drm_display_init_modeset(&drmdpy->base); return &drmdpy->base; diff --git a/src/gallium/state_trackers/egl/drm/native_drm.h b/src/gallium/state_trackers/egl/drm/native_drm.h index 7da9b45f23e..41cdc4f9d04 100644 --- a/src/gallium/state_trackers/egl/drm/native_drm.h +++ b/src/gallium/state_trackers/egl/drm/native_drm.h @@ -37,6 +37,10 @@ #include "common/native.h" #include "common/native_helper.h" +#ifdef HAVE_WAYLAND_BACKEND +#include "common/native_wayland_drm_bufmgr_helper.h" +#endif + struct drm_config; struct drm_crtc; struct drm_connector; @@ -49,6 +53,7 @@ struct drm_display { struct native_event_handler *event_handler; int fd; + char *device_name; struct drm_config *config; /* for modesetting */ @@ -59,6 +64,10 @@ struct drm_display { struct drm_surface **shown_surfaces; /* save the original settings of the CRTCs */ struct drm_crtc *saved_crtcs; + +#ifdef HAVE_WAYLAND_BACKEND + struct wl_drm *wl_server_drm; /* for EGL_WL_bind_wayland_display */ +#endif }; struct drm_config { diff --git a/src/gallium/state_trackers/egl/wayland/native_drm.c b/src/gallium/state_trackers/egl/wayland/native_drm.c index 604720f6e5f..f643c7cbbba 100644 --- a/src/gallium/state_trackers/egl/wayland/native_drm.c +++ b/src/gallium/state_trackers/egl/wayland/native_drm.c @@ -45,6 +45,8 @@ #include "wayland-drm-client-protocol.h" #include "wayland-egl-priv.h" +#include "common/native_wayland_drm_bufmgr_helper.h" + #include <xf86drm.h> #include <sys/types.h> #include <sys/stat.h> @@ -56,6 +58,7 @@ struct wayland_drm_display { struct native_event_handler *event_handler; struct wl_drm *wl_drm; + struct wl_drm *wl_server_drm; /* for EGL_WL_bind_wayland_display */ int fd; char *device_name; boolean authenticated; @@ -268,6 +271,71 @@ static struct native_display_buffer wayland_drm_display_buffer = { wayland_drm_display_export_buffer }; +static int +wayland_drm_display_authenticate(void *user_data, uint32_t magic) +{ + struct native_display *ndpy = user_data; + struct wayland_drm_display *drmdpy = wayland_drm_display(ndpy); + boolean current_authenticate, authenticated; + + current_authenticate = drmdpy->authenticated; + + wl_drm_authenticate(drmdpy->wl_drm, magic); + force_roundtrip(drmdpy->base.dpy); + authenticated = drmdpy->authenticated; + + drmdpy->authenticated = current_authenticate; + + return authenticated ? 0 : -1; +} + +static struct wayland_drm_callbacks wl_drm_callbacks = { + wayland_drm_display_authenticate, + egl_g3d_wl_drm_helper_reference_buffer, + egl_g3d_wl_drm_helper_unreference_buffer +}; + +static boolean +wayland_drm_display_bind_wayland_display(struct native_display *ndpy, + struct wl_display *wl_dpy) +{ + struct wayland_drm_display *drmdpy = wayland_drm_display(ndpy); + + if (drmdpy->wl_server_drm) + return FALSE; + + drmdpy->wl_server_drm = + wayland_drm_init(wl_dpy, drmdpy->device_name, + &wl_drm_callbacks, ndpy); + + if (!drmdpy->wl_server_drm) + return FALSE; + + return TRUE; +} + +static boolean +wayland_drm_display_unbind_wayland_display(struct native_display *ndpy, + struct wl_display *wl_dpy) +{ + struct wayland_drm_display *drmdpy = wayland_drm_display(ndpy); + + if (!drmdpy->wl_server_drm) + return FALSE; + + wayland_drm_uninit(drmdpy->wl_server_drm); + drmdpy->wl_server_drm = NULL; + + return TRUE; +} + +static struct native_display_wayland_bufmgr wayland_drm_display_wayland_bufmgr = { + wayland_drm_display_bind_wayland_display, + wayland_drm_display_unbind_wayland_display, + egl_g3d_wl_drm_common_wl_buffer_get_resource +}; + + struct wayland_display * wayland_create_drm_display(struct wl_display *dpy, struct native_event_handler *event_handler, @@ -294,6 +362,7 @@ wayland_create_drm_display(struct wl_display *dpy, } drmdpy->base.base.destroy = wayland_drm_display_destroy; drmdpy->base.base.buffer = &wayland_drm_display_buffer; + drmdpy->base.base.wayland_bufmgr = &wayland_drm_display_wayland_bufmgr; drmdpy->base.create_buffer = wayland_create_drm_buffer; diff --git a/src/gallium/state_trackers/egl/x11/native_dri2.c b/src/gallium/state_trackers/egl/x11/native_dri2.c index 5afca67a4d4..a56d43428fc 100644 --- a/src/gallium/state_trackers/egl/x11/native_dri2.c +++ b/src/gallium/state_trackers/egl/x11/native_dri2.c @@ -38,6 +38,10 @@ #include "native_x11.h" #include "x11_screen.h" +#ifdef HAVE_WAYLAND_BACKEND +#include "common/native_wayland_drm_bufmgr_helper.h" +#endif + #ifdef GLX_DIRECT_RENDERING struct dri2_display { @@ -56,6 +60,9 @@ struct dri2_display { int num_configs; struct util_hash_table *surfaces; +#ifdef HAVE_WAYLAND_BACKEND + struct wl_drm *wl_server_drm; /* for EGL_WL_bind_wayland_display */ +#endif }; struct dri2_surface { @@ -802,6 +809,65 @@ dri2_display_hash_table_compare(void *key1, void *key2) return ((char *) key1 - (char *) key2); } +static int +dri2_display_authenticate(void *user_data, uint32_t magic) +{ + struct native_display *ndpy = user_data; + struct dri2_display *dri2dpy = dri2_display(ndpy); + + return x11_screen_authenticate(dri2dpy->xscr, magic); +} + +#ifdef HAVE_WAYLAND_BACKEND + +static struct wayland_drm_callbacks wl_drm_callbacks = { + dri2_display_authenticate, + egl_g3d_wl_drm_helper_reference_buffer, + egl_g3d_wl_drm_helper_unreference_buffer +}; + +static boolean +dri2_display_bind_wayland_display(struct native_display *ndpy, + struct wl_display *wl_dpy) +{ + struct dri2_display *dri2dpy = dri2_display(ndpy); + + if (dri2dpy->wl_server_drm) + return FALSE; + + dri2dpy->wl_server_drm = wayland_drm_init(wl_dpy, + x11_screen_get_device_name(dri2dpy->xscr), + &wl_drm_callbacks, ndpy); + + if (!dri2dpy->wl_server_drm) + return FALSE; + + return TRUE; +} + +static boolean +dri2_display_unbind_wayland_display(struct native_display *ndpy, + struct wl_display *wl_dpy) +{ + struct dri2_display *dri2dpy = dri2_display(ndpy); + + if (!dri2dpy->wl_server_drm) + return FALSE; + + wayland_drm_uninit(dri2dpy->wl_server_drm); + dri2dpy->wl_server_drm = NULL; + + return TRUE; +} + +static struct native_display_wayland_bufmgr dri2_display_wayland_bufmgr = { + dri2_display_bind_wayland_display, + dri2_display_unbind_wayland_display, + egl_g3d_wl_drm_common_wl_buffer_get_resource +}; + +#endif /* HAVE_WAYLAND_BACKEND */ + struct native_display * x11_create_dri2_display(Display *dpy, struct native_event_handler *event_handler, @@ -851,6 +917,9 @@ x11_create_dri2_display(Display *dpy, dri2dpy->base.is_pixmap_supported = dri2_display_is_pixmap_supported; dri2dpy->base.create_window_surface = dri2_display_create_window_surface; dri2dpy->base.create_pixmap_surface = dri2_display_create_pixmap_surface; +#ifdef HAVE_WAYLAND_BACKEND + dri2dpy->base.wayland_bufmgr = &dri2_display_wayland_bufmgr; +#endif return &dri2dpy->base; } diff --git a/src/gallium/state_trackers/egl/x11/x11_screen.c b/src/gallium/state_trackers/egl/x11/x11_screen.c index c919b79eac8..f1cc4400ba5 100644 --- a/src/gallium/state_trackers/egl/x11/x11_screen.c +++ b/src/gallium/state_trackers/egl/x11/x11_screen.c @@ -307,6 +307,23 @@ x11_screen_enable_dri2(struct x11_screen *xscr, return xscr->dri_fd; } +char * +x11_screen_get_device_name(struct x11_screen *xscr) +{ + return xscr->dri_device; +} + +int +x11_screen_authenticate(struct x11_screen *xscr, uint32_t id) +{ + boolean authenticated; + + authenticated = DRI2Authenticate(xscr->dpy, + RootWindow(xscr->dpy, xscr->number), id); + + return authenticated ? 0 : -1; +} + /** * Create/Destroy the DRI drawable. */ diff --git a/src/gallium/state_trackers/egl/x11/x11_screen.h b/src/gallium/state_trackers/egl/x11/x11_screen.h index 2e313e0148e..acf1300e9d1 100644 --- a/src/gallium/state_trackers/egl/x11/x11_screen.h +++ b/src/gallium/state_trackers/egl/x11/x11_screen.h @@ -97,6 +97,12 @@ x11_screen_enable_dri2(struct x11_screen *xscr, x11_drawable_invalidate_buffers invalidate_buffers, void *user_data); +char * +x11_screen_get_device_name(struct x11_screen *xscr); + +int +x11_screen_authenticate(struct x11_screen *xscr, uint32_t id); + void x11_drawable_enable_dri2(struct x11_screen *xscr, Drawable drawable, boolean on); diff --git a/src/gallium/state_trackers/wgl/stw_framebuffer.c b/src/gallium/state_trackers/wgl/stw_framebuffer.c index 4033365bfbe..7a689f9977d 100644 --- a/src/gallium/state_trackers/wgl/stw_framebuffer.c +++ b/src/gallium/state_trackers/wgl/stw_framebuffer.c @@ -146,8 +146,6 @@ stw_framebuffer_get_size( struct stw_framebuffer *fb ) * maximized again. */ - assert(width == 0 && height == 0); - return; } diff --git a/src/gallium/state_trackers/xorg/xorg_exa.c b/src/gallium/state_trackers/xorg/xorg_exa.c index 91c206f1872..b072f53aa91 100644 --- a/src/gallium/state_trackers/xorg/xorg_exa.c +++ b/src/gallium/state_trackers/xorg/xorg_exa.c @@ -49,9 +49,24 @@ #include "util/u_box.h" #include "util/u_surface.h" -#define DEBUG_PRINT 0 #define ROUND_UP_TEXTURES 1 +static INLINE void +exa_debug_printf(const char *format, ...) _util_printf_format(1,2); + +static INLINE void +exa_debug_printf(const char *format, ...) +{ +#if 0 + va_list ap; + va_start(ap, format); + _debug_vprintf(format, ap); + va_end(ap); +#else + (void) format; /* silence warning */ +#endif +} + /* * Helper functions */ @@ -195,10 +210,8 @@ ExaDownloadFromScreen(PixmapPtr pPix, int x, int y, int w, int h, char *dst, if (!transfer) return FALSE; -#if DEBUG_PRINT - debug_printf("------ ExaDownloadFromScreen(%d, %d, %d, %d, %d)\n", + exa_debug_printf("------ ExaDownloadFromScreen(%d, %d, %d, %d, %d)\n", x, y, w, h, dst_pitch); -#endif util_copy_rect((unsigned char*)dst, priv->tex->format, dst_pitch, 0, 0, w, h, exa->pipe->transfer_map(exa->pipe, transfer), @@ -229,10 +242,8 @@ ExaUploadToScreen(PixmapPtr pPix, int x, int y, int w, int h, char *src, if (!transfer) return FALSE; -#if DEBUG_PRINT - debug_printf("++++++ ExaUploadToScreen(%d, %d, %d, %d, %d)\n", + exa_debug_printf("++++++ ExaUploadToScreen(%d, %d, %d, %d, %d)\n", x, y, w, h, src_pitch); -#endif util_copy_rect(exa->pipe->transfer_map(exa->pipe, transfer), priv->tex->format, transfer->stride, 0, 0, w, h, @@ -261,6 +272,8 @@ ExaPrepareAccess(PixmapPtr pPix, int index) if (!priv->tex) return FALSE; + exa_debug_printf("ExaPrepareAccess %d\n", index); + if (priv->map_count == 0) { assert(pPix->drawable.width <= priv->tex->width0); @@ -289,6 +302,8 @@ ExaPrepareAccess(PixmapPtr pPix, int index) priv->map_count++; + exa_debug_printf("ExaPrepareAccess %d prepared\n", index); + return TRUE; } @@ -308,6 +323,8 @@ ExaFinishAccess(PixmapPtr pPix, int index) if (!priv->map_transfer) return; + exa_debug_printf("ExaFinishAccess %d\n", index); + if (--priv->map_count == 0) { assert(priv->map_transfer); exa->pipe->transfer_unmap(exa->pipe, priv->map_transfer); @@ -315,6 +332,8 @@ ExaFinishAccess(PixmapPtr pPix, int index) priv->map_transfer = NULL; pPix->devPrivate.ptr = NULL; } + + exa_debug_printf("ExaFinishAccess %d finished\n", index); } /*********************************************************************** @@ -329,9 +348,8 @@ ExaPrepareSolid(PixmapPtr pPixmap, int alu, Pixel planeMask, Pixel fg) struct exa_pixmap_priv *priv = exaGetPixmapDriverPrivate(pPixmap); struct exa_context *exa = ms->exa; -#if DEBUG_PRINT - debug_printf("ExaPrepareSolid(0x%x)\n", fg); -#endif + exa_debug_printf("ExaPrepareSolid(0x%x)\n", fg); + if (!exa->accel) return FALSE; @@ -364,9 +382,7 @@ ExaSolid(PixmapPtr pPixmap, int x0, int y0, int x1, int y1) struct exa_context *exa = ms->exa; struct exa_pixmap_priv *priv = exaGetPixmapDriverPrivate(pPixmap); -#if DEBUG_PRINT - debug_printf("\tExaSolid(%d, %d, %d, %d)\n", x0, y0, x1, y1); -#endif + exa_debug_printf("\tExaSolid(%d, %d, %d, %d)\n", x0, y0, x1, y1); if (x0 == 0 && y0 == 0 && x1 == pPixmap->drawable.width && y1 == pPixmap->drawable.height) { @@ -388,8 +404,10 @@ ExaDoneSolid(PixmapPtr pPixmap) if (!priv) return; - + + exa_debug_printf("ExaDoneSolid\n"); xorg_composite_done(exa); + exa_debug_printf("ExaDoneSolid done\n"); } /*********************************************************************** @@ -406,9 +424,7 @@ ExaPrepareCopy(PixmapPtr pSrcPixmap, PixmapPtr pDstPixmap, int xdir, struct exa_pixmap_priv *priv = exaGetPixmapDriverPrivate(pDstPixmap); struct exa_pixmap_priv *src_priv = exaGetPixmapDriverPrivate(pSrcPixmap); -#if DEBUG_PRINT - debug_printf("ExaPrepareCopy\n"); -#endif + exa_debug_printf("ExaPrepareCopy\n"); if (!exa->accel) return FALSE; @@ -488,10 +504,8 @@ ExaCopy(PixmapPtr pDstPixmap, int srcX, int srcY, int dstX, int dstY, struct exa_context *exa = ms->exa; struct exa_pixmap_priv *priv = exaGetPixmapDriverPrivate(pDstPixmap); -#if DEBUG_PRINT - debug_printf("\tExaCopy(srcx=%d, srcy=%d, dstX=%d, dstY=%d, w=%d, h=%d)\n", + exa_debug_printf("\tExaCopy(srcx=%d, srcy=%d, dstX=%d, dstY=%d, w=%d, h=%d)\n", srcX, srcY, dstX, dstY, width, height); -#endif debug_assert(priv == exa->copy.dst); (void) priv; @@ -527,12 +541,16 @@ ExaDoneCopy(PixmapPtr pPixmap) if (!priv) return; + exa_debug_printf("ExaDoneCopy\n"); + renderer_draw_flush(exa->renderer); exa->copy.src = NULL; exa->copy.dst = NULL; pipe_surface_reference(&exa->copy.dst_surface, NULL); pipe_resource_reference(&exa->copy.src_texture, NULL); + + exa_debug_printf("ExaDoneCopy done\n"); } @@ -584,19 +602,15 @@ ExaCheckComposite(int op, ScrnInfoPtr pScrn = xf86Screens[pDstPicture->pDrawable->pScreen->myNum]; modesettingPtr ms = modesettingPTR(pScrn); struct exa_context *exa = ms->exa; - -#if DEBUG_PRINT - debug_printf("ExaCheckComposite(%d, %p, %p, %p) = %d\n", - op, pSrcPicture, pMaskPicture, pDstPicture, accelerated); -#endif - - if (!exa->accel) - return FALSE; - - return xorg_composite_accelerated(op, + Bool accelerated = exa->accel && xorg_composite_accelerated(op, pSrcPicture, pMaskPicture, pDstPicture); + + exa_debug_printf("ExaCheckComposite(%d, %p, %p, %p) = %d\n", + op, pSrcPicture, pMaskPicture, pDstPicture, accelerated); + + return accelerated; } @@ -613,14 +627,13 @@ ExaPrepareComposite(int op, PicturePtr pSrcPicture, if (!exa->accel) return FALSE; -#if DEBUG_PRINT - debug_printf("ExaPrepareComposite(%d, src=0x%p, mask=0x%p, dst=0x%p)\n", + exa_debug_printf("ExaPrepareComposite(%d, src=0x%p, mask=0x%p, dst=0x%p)\n", op, pSrcPicture, pMaskPicture, pDstPicture); - debug_printf("\tFormats: src(%s), mask(%s), dst(%s)\n", + exa_debug_printf("\tFormats: src(%s), mask(%s), dst(%s)\n", pSrcPicture ? render_format_name(pSrcPicture->format) : "none", pMaskPicture ? render_format_name(pMaskPicture->format) : "none", pDstPicture ? render_format_name(pDstPicture->format) : "none"); -#endif + if (!exa->pipe) XORG_FALLBACK("accel not enabled"); @@ -687,12 +700,10 @@ ExaComposite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY, struct exa_context *exa = ms->exa; struct exa_pixmap_priv *priv = exaGetPixmapDriverPrivate(pDst); -#if DEBUG_PRINT - debug_printf("\tExaComposite(src[%d,%d], mask=[%d, %d], dst=[%d, %d], dim=[%d, %d])\n", + exa_debug_printf("\tExaComposite(src[%d,%d], mask=[%d, %d], dst=[%d, %d], dim=[%d, %d])\n", srcX, srcY, maskX, maskY, dstX, dstY, width, height); - debug_printf("\t Num bound samplers = %d\n", + exa_debug_printf("\t Num bound samplers = %d\n", exa->num_bound_samplers); -#endif xorg_composite(exa, priv, srcX, srcY, maskX, maskY, dstX, dstY, width, height); diff --git a/src/gallium/targets/egl/Makefile b/src/gallium/targets/egl/Makefile index 9d76a706122..a455b61af98 100644 --- a/src/gallium/targets/egl/Makefile +++ b/src/gallium/targets/egl/Makefile @@ -49,6 +49,7 @@ endif ifneq ($(findstring wayland, $(EGL_PLATFORMS)),) egl_SYS += $(WAYLAND_LIBS) $(LIBDRM_LIB) egl_LIBS += $(TOP)/src/gallium/winsys/sw/wayland/libws_wayland.a +egl_LIBS += $(TOP)/src/egl/wayland/wayland-drm/libwayland-drm.a endif ifneq ($(findstring drm, $(EGL_PLATFORMS)),) egl_SYS += $(LIBDRM_LIB) diff --git a/src/gallium/winsys/r600/drm/evergreen_hw_context.c b/src/gallium/winsys/r600/drm/evergreen_hw_context.c index 0a5b1a09336..2a2c37ff606 100644 --- a/src/gallium/winsys/r600/drm/evergreen_hw_context.c +++ b/src/gallium/winsys/r600/drm/evergreen_hw_context.c @@ -41,432 +41,432 @@ #define GROUP_FORCE_NEW_BLOCK 0 static const struct r600_reg evergreen_config_reg_list[] = { - {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008A14_PA_CL_ENHANCE, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C00_SQ_CONFIG, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C0C_SQ_THREAD_RESOURCE_MGMT, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C20_SQ_STACK_RESOURCE_MGMT_1, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C24_SQ_STACK_RESOURCE_MGMT_2, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C28_SQ_STACK_RESOURCE_MGMT_3, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_009100_SPI_CONFIG_CNTL, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_00913C_SPI_CONFIG_CNTL_1, 0, 0, 0}, + {R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0}, + {R_008A14_PA_CL_ENHANCE, 0, 0, 0}, + {R_008C00_SQ_CONFIG, 0, 0, 0}, + {R_008C04_SQ_GPR_RESOURCE_MGMT_1, 0, 0, 0}, + {R_008C08_SQ_GPR_RESOURCE_MGMT_2, 0, 0, 0}, + {R_008C0C_SQ_THREAD_RESOURCE_MGMT, 0, 0, 0}, + {R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 0, 0, 0}, + {R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, 0, 0, 0}, + {R_008C20_SQ_STACK_RESOURCE_MGMT_1, 0, 0, 0}, + {R_008C24_SQ_STACK_RESOURCE_MGMT_2, 0, 0, 0}, + {R_008C28_SQ_STACK_RESOURCE_MGMT_3, 0, 0, 0}, + {R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0, 0, 0}, + {R_009100_SPI_CONFIG_CNTL, 0, 0, 0}, + {R_00913C_SPI_CONFIG_CNTL_1, 0, 0, 0}, }; static const struct r600_reg evergreen_ctl_const_list[] = { - {PKT3_SET_CTL_CONST, EVERGREEN_CTL_CONST_OFFSET, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0, 0}, - {PKT3_SET_CTL_CONST, EVERGREEN_CTL_CONST_OFFSET, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0, 0}, + {R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0, 0}, + {R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0, 0}, }; static const struct r600_reg evergreen_context_reg_list[] = { - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028000_DB_RENDER_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028004_DB_COUNT_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028008_DB_DEPTH_VIEW, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02800C_DB_RENDER_OVERRIDE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028010_DB_RENDER_OVERRIDE2, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028014_DB_HTILE_DATA_BASE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028028_DB_STENCIL_CLEAR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02802C_DB_DEPTH_CLEAR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028040_DB_Z_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028044_DB_STENCIL_INFO, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028048_DB_Z_READ_BASE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02804C_DB_STENCIL_READ_BASE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028050_DB_Z_WRITE_BASE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028054_DB_STENCIL_WRITE_BASE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028058_DB_DEPTH_SIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02805C_DB_DEPTH_SLICE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028200_PA_SC_WINDOW_OFFSET, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02820C_PA_SC_CLIPRECT_RULE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028210_PA_SC_CLIPRECT_0_TL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028214_PA_SC_CLIPRECT_0_BR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028230_PA_SC_EDGERULE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028238_CB_TARGET_MASK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02823C_CB_SHADER_MASK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028350_SX_MISC, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028400_VGT_MAX_VTX_INDX, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028404_VGT_MIN_VTX_INDX, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028408_VGT_INDX_OFFSET, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028414_CB_BLEND_RED, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028418_CB_BLEND_GREEN, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02841C_CB_BLEND_BLUE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028420_CB_BLEND_ALPHA, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028430_DB_STENCILREFMASK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028434_DB_STENCILREFMASK_BF, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028438_SX_ALPHA_REF, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285BC_PA_CL_UCP0_X, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285C0_PA_CL_UCP0_Y, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285C4_PA_CL_UCP0_Z, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285C8_PA_CL_UCP0_W, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285CC_PA_CL_UCP1_X, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285D0_PA_CL_UCP1_Y, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285D4_PA_CL_UCP1_Z, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285D8_PA_CL_UCP1_W, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285DC_PA_CL_UCP2_X, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285E0_PA_CL_UCP2_Y, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285E4_PA_CL_UCP2_Z, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285E8_PA_CL_UCP2_W, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285EC_PA_CL_UCP3_X, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285F0_PA_CL_UCP3_Y, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285F4_PA_CL_UCP3_Z, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285F8_PA_CL_UCP3_W, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285FC_PA_CL_UCP4_X, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028600_PA_CL_UCP4_Y, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028604_PA_CL_UCP4_Z, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028608_PA_CL_UCP4_W, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02860C_PA_CL_UCP5_X, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028610_PA_CL_UCP5_Y, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028614_PA_CL_UCP5_Z, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028618_PA_CL_UCP5_W, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02861C_SPI_VS_OUT_ID_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028620_SPI_VS_OUT_ID_1, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028624_SPI_VS_OUT_ID_2, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028628_SPI_VS_OUT_ID_3, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02862C_SPI_VS_OUT_ID_4, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028630_SPI_VS_OUT_ID_5, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028634_SPI_VS_OUT_ID_6, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028638_SPI_VS_OUT_ID_7, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02863C_SPI_VS_OUT_ID_8, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028640_SPI_VS_OUT_ID_9, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286D4_SPI_INTERP_CONTROL_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286D8_SPI_INPUT_Z, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286DC_SPI_FOG_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286E0_SPI_BARYC_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286E4_SPI_PS_IN_CONTROL_2, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286E8_SPI_COMPUTE_INPUT_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028780_CB_BLEND0_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028784_CB_BLEND1_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028788_CB_BLEND2_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02878C_CB_BLEND3_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028790_CB_BLEND4_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028794_CB_BLEND5_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028798_CB_BLEND6_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02879C_CB_BLEND7_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028800_DB_DEPTH_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02880C_DB_SHADER_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028808_CB_COLOR_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028810_PA_CL_CLIP_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028814_PA_SU_SC_MODE_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028818_PA_CL_VTE_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02881C_PA_CL_VS_OUT_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028820_PA_CL_NANINF_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028844_SQ_PGM_RESOURCES_PS, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028848_SQ_PGM_RESOURCES_2_PS, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02884C_SQ_PGM_EXPORTS_PS, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02885C_SQ_PGM_START_VS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028860_SQ_PGM_RESOURCES_VS, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028864_SQ_PGM_RESOURCES_2_VS, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0288A4_SQ_PGM_START_FS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0288A8_SQ_PGM_RESOURCES_FS, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0288EC_SQ_LDS_ALLOC_PS, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028900_SQ_ESGS_RING_ITEMSIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028904_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02891C_SQ_GS_VERT_ITEMSIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A00_PA_SU_POINT_SIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A04_PA_SU_POINT_MINMAX, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A08_PA_SU_LINE_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A14_VGT_HOS_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A2C_VGT_GROUP_DECR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A40_VGT_GS_MODE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A48_PA_SC_MODE_CNTL_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A4C_PA_SC_MODE_CNTL_1, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028AB4_VGT_REUSE_OFF, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028AB8_VGT_VTX_CNT_EN, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028ABC_DB_HTILE_SURFACE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028AC8_DB_PRELOAD_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B54_VGT_SHADER_STAGES_EN, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B70_DB_ALPHA_TO_MASK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B94_VGT_STRMOUT_CONFIG, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C00_PA_SC_LINE_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C04_PA_SC_AA_CONFIG, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C08_PA_SU_VTX_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C3C_PA_SC_AA_MASK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C60_CB_COLOR0_BASE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C64_CB_COLOR0_PITCH, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C68_CB_COLOR0_SLICE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C6C_CB_COLOR0_VIEW, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C70_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C74_CB_COLOR0_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C78_CB_COLOR0_DIM, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C9C_CB_COLOR1_BASE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CA0_CB_COLOR1_PITCH, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CA4_CB_COLOR1_SLICE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CA8_CB_COLOR1_VIEW, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CAC_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CB0_CB_COLOR1_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CB4_CB_COLOR1_DIM, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CD8_CB_COLOR2_BASE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CDC_CB_COLOR2_PITCH, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CE0_CB_COLOR2_SLICE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CE4_CB_COLOR2_VIEW, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CE8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CEC_CB_COLOR2_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CF0_CB_COLOR2_DIM, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D14_CB_COLOR3_BASE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D18_CB_COLOR3_PITCH, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D1C_CB_COLOR3_SLICE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D20_CB_COLOR3_VIEW, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D24_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D28_CB_COLOR3_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D2C_CB_COLOR3_DIM, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D50_CB_COLOR4_BASE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D54_CB_COLOR4_PITCH, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D58_CB_COLOR4_SLICE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D5C_CB_COLOR4_VIEW, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D60_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D64_CB_COLOR4_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D68_CB_COLOR4_DIM, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D8C_CB_COLOR5_BASE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D90_CB_COLOR5_PITCH, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D94_CB_COLOR5_SLICE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D98_CB_COLOR5_VIEW, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D9C_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DA0_CB_COLOR5_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DA4_CB_COLOR5_DIM, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DC8_CB_COLOR6_BASE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DCC_CB_COLOR6_PITCH, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DD0_CB_COLOR6_SLICE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DD4_CB_COLOR6_VIEW, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DD8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DDC_CB_COLOR6_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DE0_CB_COLOR6_DIM, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E04_CB_COLOR7_BASE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E08_CB_COLOR7_PITCH, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E0C_CB_COLOR7_SLICE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E10_CB_COLOR7_VIEW, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E14_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E18_CB_COLOR7_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E1C_CB_COLOR7_DIM, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E40_CB_COLOR8_BASE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E44_CB_COLOR8_PITCH, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E48_CB_COLOR8_SLICE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E4C_CB_COLOR8_VIEW, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E50_CB_COLOR8_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E54_CB_COLOR8_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E58_CB_COLOR8_DIM, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E5C_CB_COLOR9_BASE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E60_CB_COLOR9_PITCH, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E64_CB_COLOR9_SLICE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E68_CB_COLOR9_VIEW, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E6C_CB_COLOR9_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E70_CB_COLOR9_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E74_CB_COLOR9_DIM, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E78_CB_COLOR10_BASE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E7C_CB_COLOR10_PITCH, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E80_CB_COLOR10_SLICE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E84_CB_COLOR10_VIEW, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E88_CB_COLOR10_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E8C_CB_COLOR10_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E90_CB_COLOR10_DIM, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E94_CB_COLOR11_BASE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E98_CB_COLOR11_PITCH, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E9C_CB_COLOR11_SLICE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028EA0_CB_COLOR11_VIEW, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028EA4_CB_COLOR11_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028EA8_CB_COLOR11_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028EAC_CB_COLOR11_DIM, 0, 0, 0}, + {R_028000_DB_RENDER_CONTROL, 0, 0, 0}, + {R_028004_DB_COUNT_CONTROL, 0, 0, 0}, + {R_028008_DB_DEPTH_VIEW, 0, 0, 0}, + {R_02800C_DB_RENDER_OVERRIDE, 0, 0, 0}, + {R_028010_DB_RENDER_OVERRIDE2, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028014_DB_HTILE_DATA_BASE, REG_FLAG_NEED_BO, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028028_DB_STENCIL_CLEAR, 0, 0, 0}, + {R_02802C_DB_DEPTH_CLEAR, 0, 0, 0}, + {R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0}, + {R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028040_DB_Z_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028044_DB_STENCIL_INFO, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028048_DB_Z_READ_BASE, REG_FLAG_NEED_BO, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_02804C_DB_STENCIL_READ_BASE, REG_FLAG_NEED_BO, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028050_DB_Z_WRITE_BASE, REG_FLAG_NEED_BO, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028054_DB_STENCIL_WRITE_BASE, REG_FLAG_NEED_BO, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028058_DB_DEPTH_SIZE, 0, 0, 0}, + {R_02805C_DB_DEPTH_SLICE, 0, 0, 0}, + {R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0}, + {R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0}, + {R_028200_PA_SC_WINDOW_OFFSET, 0, 0, 0}, + {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0}, + {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0}, + {R_02820C_PA_SC_CLIPRECT_RULE, 0, 0, 0}, + {R_028210_PA_SC_CLIPRECT_0_TL, 0, 0, 0}, + {R_028214_PA_SC_CLIPRECT_0_BR, 0, 0, 0}, + {R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0}, + {R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0}, + {R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0}, + {R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0}, + {R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0}, + {R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0}, + {R_028230_PA_SC_EDGERULE, 0, 0, 0}, + {R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0, 0}, + {R_028238_CB_TARGET_MASK, 0, 0, 0}, + {R_02823C_CB_SHADER_MASK, 0, 0, 0}, + {R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0}, + {R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0}, + {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0}, + {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0}, + {R_028350_SX_MISC, 0, 0, 0}, + {R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0}, + {R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0}, + {R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0}, + {R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0}, + {R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0}, + {R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0}, + {R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0}, + {R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0}, + {R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0}, + {R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0}, + {R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0}, + {R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0}, + {R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0}, + {R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0}, + {R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0}, + {R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0}, + {R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0}, + {R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0}, + {R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0}, + {R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0}, + {R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0}, + {R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0}, + {R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0}, + {R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0}, + {R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0}, + {R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0}, + {R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0}, + {R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0}, + {R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0}, + {R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0}, + {R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0}, + {R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0}, + {R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0}, + {R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0}, + {R_028400_VGT_MAX_VTX_INDX, 0, 0, 0}, + {R_028404_VGT_MIN_VTX_INDX, 0, 0, 0}, + {R_028408_VGT_INDX_OFFSET, 0, 0, 0}, + {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0}, + {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0}, + {R_028414_CB_BLEND_RED, 0, 0, 0}, + {R_028418_CB_BLEND_GREEN, 0, 0, 0}, + {R_02841C_CB_BLEND_BLUE, 0, 0, 0}, + {R_028420_CB_BLEND_ALPHA, 0, 0, 0}, + {R_028430_DB_STENCILREFMASK, 0, 0, 0}, + {R_028434_DB_STENCILREFMASK_BF, 0, 0, 0}, + {R_028438_SX_ALPHA_REF, 0, 0, 0}, + {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0}, + {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0}, + {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0}, + {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0}, + {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0}, + {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0}, + {R_0285BC_PA_CL_UCP0_X, 0, 0, 0}, + {R_0285C0_PA_CL_UCP0_Y, 0, 0, 0}, + {R_0285C4_PA_CL_UCP0_Z, 0, 0, 0}, + {R_0285C8_PA_CL_UCP0_W, 0, 0, 0}, + {R_0285CC_PA_CL_UCP1_X, 0, 0, 0}, + {R_0285D0_PA_CL_UCP1_Y, 0, 0, 0}, + {R_0285D4_PA_CL_UCP1_Z, 0, 0, 0}, + {R_0285D8_PA_CL_UCP1_W, 0, 0, 0}, + {R_0285DC_PA_CL_UCP2_X, 0, 0, 0}, + {R_0285E0_PA_CL_UCP2_Y, 0, 0, 0}, + {R_0285E4_PA_CL_UCP2_Z, 0, 0, 0}, + {R_0285E8_PA_CL_UCP2_W, 0, 0, 0}, + {R_0285EC_PA_CL_UCP3_X, 0, 0, 0}, + {R_0285F0_PA_CL_UCP3_Y, 0, 0, 0}, + {R_0285F4_PA_CL_UCP3_Z, 0, 0, 0}, + {R_0285F8_PA_CL_UCP3_W, 0, 0, 0}, + {R_0285FC_PA_CL_UCP4_X, 0, 0, 0}, + {R_028600_PA_CL_UCP4_Y, 0, 0, 0}, + {R_028604_PA_CL_UCP4_Z, 0, 0, 0}, + {R_028608_PA_CL_UCP4_W, 0, 0, 0}, + {R_02860C_PA_CL_UCP5_X, 0, 0, 0}, + {R_028610_PA_CL_UCP5_Y, 0, 0, 0}, + {R_028614_PA_CL_UCP5_Z, 0, 0, 0}, + {R_028618_PA_CL_UCP5_W, 0, 0, 0}, + {R_02861C_SPI_VS_OUT_ID_0, 0, 0, 0}, + {R_028620_SPI_VS_OUT_ID_1, 0, 0, 0}, + {R_028624_SPI_VS_OUT_ID_2, 0, 0, 0}, + {R_028628_SPI_VS_OUT_ID_3, 0, 0, 0}, + {R_02862C_SPI_VS_OUT_ID_4, 0, 0, 0}, + {R_028630_SPI_VS_OUT_ID_5, 0, 0, 0}, + {R_028634_SPI_VS_OUT_ID_6, 0, 0, 0}, + {R_028638_SPI_VS_OUT_ID_7, 0, 0, 0}, + {R_02863C_SPI_VS_OUT_ID_8, 0, 0, 0}, + {R_028640_SPI_VS_OUT_ID_9, 0, 0, 0}, + {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0}, + {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0}, + {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0}, + {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0}, + {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0}, + {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0}, + {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0}, + {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0}, + {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0}, + {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0}, + {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0}, + {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0}, + {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0}, + {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0}, + {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0}, + {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0}, + {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0}, + {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0}, + {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0}, + {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0}, + {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0}, + {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0}, + {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0}, + {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0}, + {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0}, + {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0}, + {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0}, + {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0}, + {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0}, + {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0}, + {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0}, + {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0}, + {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0}, + {R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0}, + {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0}, + {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0, 0}, + {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0, 0}, + {R_0286D8_SPI_INPUT_Z, 0, 0, 0}, + {R_0286DC_SPI_FOG_CNTL, 0, 0, 0}, + {R_0286E0_SPI_BARYC_CNTL, 0, 0, 0}, + {R_0286E4_SPI_PS_IN_CONTROL_2, 0, 0, 0}, + {R_0286E8_SPI_COMPUTE_INPUT_CNTL, 0, 0, 0}, + {R_028780_CB_BLEND0_CONTROL, 0, 0, 0}, + {R_028784_CB_BLEND1_CONTROL, 0, 0, 0}, + {R_028788_CB_BLEND2_CONTROL, 0, 0, 0}, + {R_02878C_CB_BLEND3_CONTROL, 0, 0, 0}, + {R_028790_CB_BLEND4_CONTROL, 0, 0, 0}, + {R_028794_CB_BLEND5_CONTROL, 0, 0, 0}, + {R_028798_CB_BLEND6_CONTROL, 0, 0, 0}, + {R_02879C_CB_BLEND7_CONTROL, 0, 0, 0}, + {R_028800_DB_DEPTH_CONTROL, 0, 0, 0}, + {R_02880C_DB_SHADER_CONTROL, 0, 0, 0}, + {R_028808_CB_COLOR_CONTROL, 0, 0, 0}, + {R_028810_PA_CL_CLIP_CNTL, 0, 0, 0}, + {R_028814_PA_SU_SC_MODE_CNTL, 0, 0, 0}, + {R_028818_PA_CL_VTE_CNTL, 0, 0, 0}, + {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0, 0}, + {R_028820_PA_CL_NANINF_CNTL, 0, 0, 0}, + {R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, 0, 0, 0}, + {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {R_028844_SQ_PGM_RESOURCES_PS, 0, 0, 0}, + {R_028848_SQ_PGM_RESOURCES_2_PS, 0, 0, 0}, + {R_02884C_SQ_PGM_EXPORTS_PS, 0, 0, 0}, + {R_02885C_SQ_PGM_START_VS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {R_028860_SQ_PGM_RESOURCES_VS, 0, 0, 0}, + {R_028864_SQ_PGM_RESOURCES_2_VS, 0, 0, 0}, + {R_0288A4_SQ_PGM_START_FS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {R_0288A8_SQ_PGM_RESOURCES_FS, 0, 0, 0}, + {R_0288EC_SQ_LDS_ALLOC_PS, 0, 0, 0}, + {R_028900_SQ_ESGS_RING_ITEMSIZE, 0, 0, 0}, + {R_028904_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0}, + {R_028908_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0}, + {R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0}, + {R_028910_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0}, + {R_028914_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0}, + {R_02891C_SQ_GS_VERT_ITEMSIZE, 0, 0, 0}, + {R_028920_SQ_GS_VERT_ITEMSIZE_1, 0, 0, 0}, + {R_028924_SQ_GS_VERT_ITEMSIZE_2, 0, 0, 0}, + {R_028928_SQ_GS_VERT_ITEMSIZE_3, 0, 0, 0}, + {R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {R_028A00_PA_SU_POINT_SIZE, 0, 0, 0}, + {R_028A04_PA_SU_POINT_MINMAX, 0, 0, 0}, + {R_028A08_PA_SU_LINE_CNTL, 0, 0, 0}, + {R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0, 0}, + {R_028A14_VGT_HOS_CNTL, 0, 0, 0}, + {R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0}, + {R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0}, + {R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0}, + {R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0}, + {R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0}, + {R_028A2C_VGT_GROUP_DECR, 0, 0, 0}, + {R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0}, + {R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0}, + {R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0}, + {R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0}, + {R_028A40_VGT_GS_MODE, 0, 0, 0}, + {R_028A48_PA_SC_MODE_CNTL_0, 0, 0, 0}, + {R_028A4C_PA_SC_MODE_CNTL_1, 0, 0, 0}, + {R_028AB4_VGT_REUSE_OFF, 0, 0, 0}, + {R_028AB8_VGT_VTX_CNT_EN, 0, 0, 0}, + {R_028ABC_DB_HTILE_SURFACE, 0, 0, 0}, + {R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0, 0, 0}, + {R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0}, + {R_028AC8_DB_PRELOAD_CONTROL, 0, 0, 0}, + {R_028B54_VGT_SHADER_STAGES_EN, 0, 0, 0}, + {R_028B70_DB_ALPHA_TO_MASK, 0, 0, 0}, + {R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0, 0}, + {R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0}, + {R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0}, + {R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0}, + {R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0}, + {R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0}, + {R_028B94_VGT_STRMOUT_CONFIG, 0, 0, 0}, + {R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0, 0, 0}, + {R_028C00_PA_SC_LINE_CNTL, 0, 0, 0}, + {R_028C04_PA_SC_AA_CONFIG, 0, 0, 0}, + {R_028C08_PA_SU_VTX_CNTL, 0, 0, 0}, + {R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0}, + {R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0}, + {R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0}, + {R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0, 0}, + {R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0, 0}, + {R_028C3C_PA_SC_AA_MASK, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028C60_CB_COLOR0_BASE, REG_FLAG_NEED_BO, 0, 0}, + {R_028C64_CB_COLOR0_PITCH, 0, 0, 0}, + {R_028C68_CB_COLOR0_SLICE, 0, 0, 0}, + {R_028C6C_CB_COLOR0_VIEW, 0, 0, 0}, + {R_028C70_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_028C74_CB_COLOR0_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, + {R_028C78_CB_COLOR0_DIM, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028C9C_CB_COLOR1_BASE, REG_FLAG_NEED_BO, 0, 0}, + {R_028CA0_CB_COLOR1_PITCH, 0, 0, 0}, + {R_028CA4_CB_COLOR1_SLICE, 0, 0, 0}, + {R_028CA8_CB_COLOR1_VIEW, 0, 0, 0}, + {R_028CAC_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_028CB0_CB_COLOR1_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, + {R_028CB4_CB_COLOR1_DIM, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028CD8_CB_COLOR2_BASE, REG_FLAG_NEED_BO, 0, 0}, + {R_028CDC_CB_COLOR2_PITCH, 0, 0, 0}, + {R_028CE0_CB_COLOR2_SLICE, 0, 0, 0}, + {R_028CE4_CB_COLOR2_VIEW, 0, 0, 0}, + {R_028CE8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_028CEC_CB_COLOR2_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, + {R_028CF0_CB_COLOR2_DIM, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028D14_CB_COLOR3_BASE, REG_FLAG_NEED_BO, 0, 0}, + {R_028D18_CB_COLOR3_PITCH, 0, 0, 0}, + {R_028D1C_CB_COLOR3_SLICE, 0, 0, 0}, + {R_028D20_CB_COLOR3_VIEW, 0, 0, 0}, + {R_028D24_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_028D28_CB_COLOR3_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, + {R_028D2C_CB_COLOR3_DIM, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028D50_CB_COLOR4_BASE, REG_FLAG_NEED_BO, 0, 0}, + {R_028D54_CB_COLOR4_PITCH, 0, 0, 0}, + {R_028D58_CB_COLOR4_SLICE, 0, 0, 0}, + {R_028D5C_CB_COLOR4_VIEW, 0, 0, 0}, + {R_028D60_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_028D64_CB_COLOR4_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, + {R_028D68_CB_COLOR4_DIM, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028D8C_CB_COLOR5_BASE, REG_FLAG_NEED_BO, 0, 0}, + {R_028D90_CB_COLOR5_PITCH, 0, 0, 0}, + {R_028D94_CB_COLOR5_SLICE, 0, 0, 0}, + {R_028D98_CB_COLOR5_VIEW, 0, 0, 0}, + {R_028D9C_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_028DA0_CB_COLOR5_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, + {R_028DA4_CB_COLOR5_DIM, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028DC8_CB_COLOR6_BASE, REG_FLAG_NEED_BO, 0, 0}, + {R_028DCC_CB_COLOR6_PITCH, 0, 0, 0}, + {R_028DD0_CB_COLOR6_SLICE, 0, 0, 0}, + {R_028DD4_CB_COLOR6_VIEW, 0, 0, 0}, + {R_028DD8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_028DDC_CB_COLOR6_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, + {R_028DE0_CB_COLOR6_DIM, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028E04_CB_COLOR7_BASE, REG_FLAG_NEED_BO, 0, 0}, + {R_028E08_CB_COLOR7_PITCH, 0, 0, 0}, + {R_028E0C_CB_COLOR7_SLICE, 0, 0, 0}, + {R_028E10_CB_COLOR7_VIEW, 0, 0, 0}, + {R_028E14_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_028E18_CB_COLOR7_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, + {R_028E1C_CB_COLOR7_DIM, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028E40_CB_COLOR8_BASE, REG_FLAG_NEED_BO, 0, 0}, + {R_028E44_CB_COLOR8_PITCH, 0, 0, 0}, + {R_028E48_CB_COLOR8_SLICE, 0, 0, 0}, + {R_028E4C_CB_COLOR8_VIEW, 0, 0, 0}, + {R_028E50_CB_COLOR8_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_028E54_CB_COLOR8_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, + {R_028E58_CB_COLOR8_DIM, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028E5C_CB_COLOR9_BASE, REG_FLAG_NEED_BO, 0, 0}, + {R_028E60_CB_COLOR9_PITCH, 0, 0, 0}, + {R_028E64_CB_COLOR9_SLICE, 0, 0, 0}, + {R_028E68_CB_COLOR9_VIEW, 0, 0, 0}, + {R_028E6C_CB_COLOR9_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_028E70_CB_COLOR9_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, + {R_028E74_CB_COLOR9_DIM, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028E78_CB_COLOR10_BASE, REG_FLAG_NEED_BO, 0, 0}, + {R_028E7C_CB_COLOR10_PITCH, 0, 0, 0}, + {R_028E80_CB_COLOR10_SLICE, 0, 0, 0}, + {R_028E84_CB_COLOR10_VIEW, 0, 0, 0}, + {R_028E88_CB_COLOR10_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_028E8C_CB_COLOR10_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, + {R_028E90_CB_COLOR10_DIM, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028E94_CB_COLOR11_BASE, REG_FLAG_NEED_BO, 0, 0}, + {R_028E98_CB_COLOR11_PITCH, 0, 0, 0}, + {R_028E9C_CB_COLOR11_SLICE, 0, 0, 0}, + {R_028EA0_CB_COLOR11_VIEW, 0, 0, 0}, + {R_028EA4_CB_COLOR11_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_028EA8_CB_COLOR11_ATTRIB, REG_FLAG_NEED_BO, 0, 0}, + {R_028EAC_CB_COLOR11_DIM, 0, 0, 0}, }; /* SHADER RESOURCE R600/R700 */ static int evergreen_state_resource_init(struct r600_context *ctx, u32 offset) { struct r600_reg r600_shader_resource[] = { - {PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_030000_RESOURCE0_WORD0, 0, 0, 0}, - {PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_030004_RESOURCE0_WORD1, 0, 0, 0}, - {PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_030008_RESOURCE0_WORD2, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF}, - {PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_03000C_RESOURCE0_WORD3, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF}, - {PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_030010_RESOURCE0_WORD4, 0, 0, 0}, - {PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_030014_RESOURCE0_WORD5, 0, 0, 0}, - {PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_030018_RESOURCE0_WORD6, 0, 0, 0}, - {PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_03001C_RESOURCE0_WORD7, 0, 0, 0}, + {R_030000_RESOURCE0_WORD0, 0, 0, 0}, + {R_030004_RESOURCE0_WORD1, 0, 0, 0}, + {R_030008_RESOURCE0_WORD2, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF}, + {R_03000C_RESOURCE0_WORD3, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF}, + {R_030010_RESOURCE0_WORD4, 0, 0, 0}, + {R_030014_RESOURCE0_WORD5, 0, 0, 0}, + {R_030018_RESOURCE0_WORD6, 0, 0, 0}, + {R_03001C_RESOURCE0_WORD7, 0, 0, 0}, }; unsigned nreg = Elements(r600_shader_resource); for (int i = 0; i < nreg; i++) { r600_shader_resource[i].offset += offset; } - return r600_context_add_block(ctx, r600_shader_resource, nreg); + return r600_context_add_block(ctx, r600_shader_resource, nreg, PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET); } /* SHADER SAMPLER R600/R700 */ static int r600_state_sampler_init(struct r600_context *ctx, u32 offset) { struct r600_reg r600_shader_sampler[] = { - {PKT3_SET_SAMPLER, EVERGREEN_SAMPLER_OFFSET, R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0}, - {PKT3_SET_SAMPLER, EVERGREEN_SAMPLER_OFFSET, R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0, 0}, - {PKT3_SET_SAMPLER, EVERGREEN_SAMPLER_OFFSET, R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0, 0}, + {R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0}, + {R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0, 0}, + {R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0, 0}, }; unsigned nreg = Elements(r600_shader_sampler); for (int i = 0; i < nreg; i++) { r600_shader_sampler[i].offset += offset; } - return r600_context_add_block(ctx, r600_shader_sampler, nreg); + return r600_context_add_block(ctx, r600_shader_sampler, nreg, PKT3_SET_SAMPLER, EVERGREEN_SAMPLER_OFFSET); } /* SHADER SAMPLER BORDER R600/R700 */ static int evergreen_state_sampler_border_init(struct r600_context *ctx, u32 offset, unsigned id) { struct r600_reg r600_shader_sampler_border[] = { - {PKT3_SET_CONFIG_REG, 0, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, 0, R_00A404_TD_PS_SAMPLER0_BORDER_RED, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, 0, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, 0, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, 0, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0, 0}, + {R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0, 0, 0}, + {R_00A404_TD_PS_SAMPLER0_BORDER_RED, 0, 0, 0}, + {R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0, 0}, + {R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0, 0}, + {R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0, 0}, }; unsigned nreg = Elements(r600_shader_sampler_border); unsigned fake_offset = (offset - R_00A400_TD_PS_SAMPLER0_BORDER_INDEX) * 0x100 + 0x40000 + id * 0x1C; @@ -478,7 +478,7 @@ static int evergreen_state_sampler_border_init(struct r600_context *ctx, u32 off r600_shader_sampler_border[i].offset -= R_00A400_TD_PS_SAMPLER0_BORDER_INDEX; r600_shader_sampler_border[i].offset += fake_offset; } - r = r600_context_add_block(ctx, r600_shader_sampler_border, nreg); + r = r600_context_add_block(ctx, r600_shader_sampler_border, nreg, PKT3_SET_CONFIG_REG, 0); if (r) { return r; } @@ -496,13 +496,12 @@ static int evergreen_loop_const_init(struct r600_context *ctx, u32 offset) int i; for (i = 0; i < nreg; i++) { - r600_loop_consts[i].opcode = PKT3_SET_LOOP_CONST; - r600_loop_consts[i].offset_base = EVERGREEN_LOOP_CONST_OFFSET; r600_loop_consts[i].offset = EVERGREEN_LOOP_CONST_OFFSET + ((offset + i) * 4); r600_loop_consts[i].flags = REG_FLAG_DIRTY_ALWAYS; r600_loop_consts[i].flush_flags = 0; + r600_loop_consts[i].flush_mask = 0; } - return r600_context_add_block(ctx, r600_loop_consts, nreg); + return r600_context_add_block(ctx, r600_loop_consts, nreg, PKT3_SET_LOOP_CONST, EVERGREEN_LOOP_CONST_OFFSET); } int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon) @@ -513,29 +512,23 @@ int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon) ctx->radeon = radeon; LIST_INITHEAD(&ctx->query_list); - /* initialize hash */ - ctx->hash_size = 19; - ctx->hash_shift = 11; - for (int i = 0; i < 256; i++) { - ctx->range[i].start_offset = i << ctx->hash_shift; - ctx->range[i].end_offset = ((i + 1) << ctx->hash_shift) - 1; - ctx->range[i].blocks = calloc(1 << ctx->hash_shift, sizeof(void*)); - if (ctx->range[i].blocks == NULL) { - return -ENOMEM; - } + ctx->range = calloc(NUM_RANGES, sizeof(struct r600_range)); + if (!ctx->range) { + r = -ENOMEM; + goto out_err; } /* add blocks */ r = r600_context_add_block(ctx, evergreen_config_reg_list, - Elements(evergreen_config_reg_list)); + Elements(evergreen_config_reg_list), PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET); if (r) goto out_err; r = r600_context_add_block(ctx, evergreen_context_reg_list, - Elements(evergreen_context_reg_list)); + Elements(evergreen_context_reg_list), PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET); if (r) goto out_err; r = r600_context_add_block(ctx, evergreen_ctl_const_list, - Elements(evergreen_ctl_const_list)); + Elements(evergreen_ctl_const_list), PKT3_SET_CTL_CONST, EVERGREEN_CTL_CONST_OFFSET); if (r) goto out_err; @@ -588,17 +581,9 @@ int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon) /* VS loop const */ evergreen_loop_const_init(ctx, 32); - /* setup block table */ - ctx->blocks = calloc(ctx->nblocks, sizeof(void*)); - for (int i = 0, c = 0; i < 256; i++) { - for (int j = 0; j < (1 << ctx->hash_shift); j++) { - if (ctx->range[i].blocks[j]) { - assert(c < ctx->nblocks); - ctx->blocks[c++] = ctx->range[i].blocks[j]; - j += (ctx->range[i].blocks[j]->nreg << 2) - 1; - } - } - } + r = r600_setup_block_table(ctx); + if (r) + goto out_err; /* allocate cs variables */ ctx->nreloc = RADEON_CTX_MAX_PM4; diff --git a/src/gallium/winsys/r600/drm/r600_hw_context.c b/src/gallium/winsys/r600/drm/r600_hw_context.c index 34ea2a6bacb..0618d2329e6 100644 --- a/src/gallium/winsys/r600/drm/r600_hw_context.c +++ b/src/gallium/winsys/r600/drm/r600_hw_context.c @@ -66,7 +66,8 @@ static void INLINE r600_context_fence_wraparound(struct r600_context *ctx, unsig } } -int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg) +int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg, + unsigned opcode, unsigned offset_base) { struct r600_block *block; struct r600_range *range; @@ -102,14 +103,20 @@ int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, ctx->nblocks++; for (int j = 0; j < n; j++) { range = &ctx->range[CTX_RANGE_ID(ctx, reg[i + j].offset)]; + /* create block table if it doesn't exist */ + if (!range->blocks) + range->blocks = calloc(1 << HASH_SHIFT, sizeof(void *)); + if (!range->blocks) + return -1; + range->blocks[CTX_BLOCK_ID(ctx, reg[i + j].offset)] = block; } /* initialize block */ block->status |= R600_BLOCK_STATUS_DIRTY; /* dirty all blocks at start */ block->start_offset = reg[i].offset; - block->pm4[block->pm4_ndwords++] = PKT3(reg[i].opcode, n, 0); - block->pm4[block->pm4_ndwords++] = (block->start_offset - reg[i].offset_base) >> 2; + block->pm4[block->pm4_ndwords++] = PKT3(opcode, n, 0); + block->pm4[block->pm4_ndwords++] = (block->start_offset - offset_base) >> 2; block->reg = &block->pm4[block->pm4_ndwords]; block->pm4_ndwords += n; block->nreg = n; @@ -155,427 +162,427 @@ int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, /* R600/R700 configuration */ static const struct r600_reg r600_config_reg_list[] = { - {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C00_SQ_CONFIG, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C0C_SQ_THREAD_RESOURCE_MGMT, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C10_SQ_STACK_RESOURCE_MGMT_1, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C14_SQ_STACK_RESOURCE_MGMT_2, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009508_TA_CNTL_AUX, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009714_VC_ENHANCE, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009830_DB_DEBUG, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009838_DB_WATERMARKS, 0, 0, 0}, + {R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0}, + {R_008C00_SQ_CONFIG, 0, 0, 0}, + {R_008C04_SQ_GPR_RESOURCE_MGMT_1, 0, 0, 0}, + {R_008C08_SQ_GPR_RESOURCE_MGMT_2, 0, 0, 0}, + {R_008C0C_SQ_THREAD_RESOURCE_MGMT, 0, 0, 0}, + {R_008C10_SQ_STACK_RESOURCE_MGMT_1, 0, 0, 0}, + {R_008C14_SQ_STACK_RESOURCE_MGMT_2, 0, 0, 0}, + {R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0, 0, 0}, + {R_009508_TA_CNTL_AUX, 0, 0, 0}, + {R_009714_VC_ENHANCE, 0, 0, 0}, + {R_009830_DB_DEBUG, 0, 0, 0}, + {R_009838_DB_WATERMARKS, 0, 0, 0}, }; static const struct r600_reg r600_ctl_const_list[] = { - {PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0, 0}, - {PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0, 0}, + {R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0, 0}, + {R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0, 0}, }; static const struct r600_reg r600_context_reg_list[] = { - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028350_SX_MISC, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A14_VGT_HOS_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A2C_VGT_GROUP_DECR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A40_VGT_GS_MODE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A4C_PA_SC_MODE_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AB0_VGT_STRMOUT_EN, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AB4_VGT_REUSE_OFF, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AB8_VGT_VTX_CNT_EN, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028B20_VGT_STRMOUT_BUFFER_EN, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028028_DB_STENCIL_CLEAR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02802C_DB_DEPTH_CLEAR, 0, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028040_CB_COLOR0_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(0), 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A0_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028060_CB_COLOR0_SIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028080_CB_COLOR0_VIEW, 0, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280E0_CB_COLOR0_FRAG, REG_FLAG_NEED_BO, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280C0_CB_COLOR0_TILE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028100_CB_COLOR0_MASK, 0, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028044_CB_COLOR1_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(1), 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A4_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028064_CB_COLOR1_SIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028084_CB_COLOR1_VIEW, 0, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280E4_CB_COLOR1_FRAG, REG_FLAG_NEED_BO, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280C4_CB_COLOR1_TILE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028104_CB_COLOR1_MASK, 0, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028048_CB_COLOR2_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(2), 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028068_CB_COLOR2_SIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028088_CB_COLOR2_VIEW, 0, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280E8_CB_COLOR2_FRAG, REG_FLAG_NEED_BO, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280C8_CB_COLOR2_TILE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028108_CB_COLOR2_MASK, 0, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02804C_CB_COLOR3_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(3), 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280AC_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02806C_CB_COLOR3_SIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02808C_CB_COLOR3_VIEW, 0, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280EC_CB_COLOR3_FRAG, REG_FLAG_NEED_BO, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280CC_CB_COLOR3_TILE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02810C_CB_COLOR3_MASK, 0, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028050_CB_COLOR4_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(4), 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B0_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028070_CB_COLOR4_SIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028090_CB_COLOR4_VIEW, 0, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280F0_CB_COLOR4_FRAG, REG_FLAG_NEED_BO, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280D0_CB_COLOR4_TILE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028110_CB_COLOR4_MASK, 0, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028054_CB_COLOR5_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(5), 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B4_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028074_CB_COLOR5_SIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028094_CB_COLOR5_VIEW, 0, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280F4_CB_COLOR5_FRAG, REG_FLAG_NEED_BO, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280D4_CB_COLOR5_TILE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028114_CB_COLOR5_MASK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028058_CB_COLOR6_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(6), 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028078_CB_COLOR6_SIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028098_CB_COLOR6_VIEW, 0, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280F8_CB_COLOR6_FRAG, REG_FLAG_NEED_BO, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280D8_CB_COLOR6_TILE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028118_CB_COLOR6_MASK, 0, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02805C_CB_COLOR7_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(7), 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280BC_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02807C_CB_COLOR7_SIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02809C_CB_COLOR7_VIEW, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280FC_CB_COLOR7_FRAG, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280DC_CB_COLOR7_TILE, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02811C_CB_COLOR7_MASK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028120_CB_CLEAR_RED, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028124_CB_CLEAR_GREEN, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028128_CB_CLEAR_BLUE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02812C_CB_CLEAR_ALPHA, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02823C_CB_SHADER_MASK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028238_CB_TARGET_MASK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028414_CB_BLEND_RED, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028418_CB_BLEND_GREEN, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02841C_CB_BLEND_BLUE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028420_CB_BLEND_ALPHA, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028424_CB_FOG_RED, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028428_CB_FOG_GREEN, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02842C_CB_FOG_BLUE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028430_DB_STENCILREFMASK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028434_DB_STENCILREFMASK_BF, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028438_SX_ALPHA_REF, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286DC_SPI_FOG_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286E0_SPI_FOG_FUNC_SCALE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286E4_SPI_FOG_FUNC_BIAS, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028780_CB_BLEND0_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028784_CB_BLEND1_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028788_CB_BLEND2_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02878C_CB_BLEND3_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028790_CB_BLEND4_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028794_CB_BLEND5_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028798_CB_BLEND6_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02879C_CB_BLEND7_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0287A0_CB_SHADER_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028800_DB_DEPTH_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028804_CB_BLEND_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028808_CB_COLOR_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02880C_DB_SHADER_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C04_PA_SC_AA_CONFIG, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C30_CB_CLRCMP_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C34_CB_CLRCMP_SRC, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C38_CB_CLRCMP_DST, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C3C_CB_CLRCMP_MSK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C48_PA_SC_AA_MASK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D44_DB_ALPHA_TO_MASK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02800C_DB_DEPTH_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_DEPTH, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028000_DB_DEPTH_SIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028004_DB_DEPTH_VIEW, 0, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028010_DB_DEPTH_INFO, REG_FLAG_NEED_BO, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D0C_DB_RENDER_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D10_DB_RENDER_OVERRIDE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D24_DB_HTILE_SURFACE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D30_DB_PRELOAD_CONTROL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D34_DB_PREFETCH_LIMIT, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028200_PA_SC_WINDOW_OFFSET, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02820C_PA_SC_CLIPRECT_RULE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028210_PA_SC_CLIPRECT_0_TL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028214_PA_SC_CLIPRECT_0_BR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028230_PA_SC_EDGERULE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286D4_SPI_INTERP_CONTROL_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028810_PA_CL_CLIP_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028814_PA_SU_SC_MODE_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028818_PA_CL_VTE_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02881C_PA_CL_VS_OUT_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028820_PA_CL_NANINF_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A00_PA_SU_POINT_SIZE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A04_PA_SU_POINT_MINMAX, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A08_PA_SU_LINE_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A0C_PA_SC_LINE_STIPPLE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A48_PA_SC_MPASS_PS_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C00_PA_SC_LINE_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C08_PA_SU_VTX_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E20_PA_CL_UCP0_X, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E24_PA_CL_UCP0_Y, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E28_PA_CL_UCP0_Z, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E2C_PA_CL_UCP0_W, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E30_PA_CL_UCP1_X, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E34_PA_CL_UCP1_Y, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E38_PA_CL_UCP1_Z, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E3C_PA_CL_UCP1_W, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E40_PA_CL_UCP2_X, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E44_PA_CL_UCP2_Y, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E48_PA_CL_UCP2_Z, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E4C_PA_CL_UCP2_W, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E50_PA_CL_UCP3_X, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E54_PA_CL_UCP3_Y, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E58_PA_CL_UCP3_Z, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E5C_PA_CL_UCP3_W, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E60_PA_CL_UCP4_X, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E64_PA_CL_UCP4_Y, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E68_PA_CL_UCP4_Z, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E6C_PA_CL_UCP4_W, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E70_PA_CL_UCP5_X, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E74_PA_CL_UCP5_Y, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E78_PA_CL_UCP5_Z, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E7C_PA_CL_UCP5_W, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028614_SPI_VS_OUT_ID_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028618_SPI_VS_OUT_ID_1, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02861C_SPI_VS_OUT_ID_2, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028620_SPI_VS_OUT_ID_3, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028624_SPI_VS_OUT_ID_4, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028628_SPI_VS_OUT_ID_5, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02862C_SPI_VS_OUT_ID_6, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028630_SPI_VS_OUT_ID_7, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028634_SPI_VS_OUT_ID_8, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028638_SPI_VS_OUT_ID_9, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028858_SQ_PGM_START_VS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028868_SQ_PGM_RESOURCES_VS, 0, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028894_SQ_PGM_START_FS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288D0_SQ_PGM_CF_OFFSET_VS, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286D8_SPI_INPUT_Z, 0, 0, 0}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, - {0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028850_SQ_PGM_RESOURCES_PS, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028854_SQ_PGM_EXPORTS_PS, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288CC_SQ_PGM_CF_OFFSET_PS, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028400_VGT_MAX_VTX_INDX, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028404_VGT_MIN_VTX_INDX, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028408_VGT_INDX_OFFSET, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A84_VGT_PRIMITIVEID_EN, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0, 0, 0}, - {PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0, 0, 0}, + {R_028350_SX_MISC, 0, 0, 0}, + {R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0}, + {R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0, 0, 0}, + {R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0}, + {R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0}, + {R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0}, + {R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0}, + {R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0}, + {R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0, 0, 0}, + {R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0, 0, 0}, + {R_0288C8_SQ_GS_VERT_ITEMSIZE, 0, 0, 0}, + {R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0, 0}, + {R_028A14_VGT_HOS_CNTL, 0, 0, 0}, + {R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0}, + {R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0}, + {R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0}, + {R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0}, + {R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0}, + {R_028A2C_VGT_GROUP_DECR, 0, 0, 0}, + {R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0}, + {R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0}, + {R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0}, + {R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0}, + {R_028A40_VGT_GS_MODE, 0, 0, 0}, + {R_028A4C_PA_SC_MODE_CNTL, 0, 0, 0}, + {R_028AB0_VGT_STRMOUT_EN, 0, 0, 0}, + {R_028AB4_VGT_REUSE_OFF, 0, 0, 0}, + {R_028AB8_VGT_VTX_CNT_EN, 0, 0, 0}, + {R_028B20_VGT_STRMOUT_BUFFER_EN, 0, 0, 0}, + {R_028028_DB_STENCIL_CLEAR, 0, 0, 0}, + {R_02802C_DB_DEPTH_CLEAR, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028040_CB_COLOR0_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(0), 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280A0_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_028060_CB_COLOR0_SIZE, 0, 0, 0}, + {R_028080_CB_COLOR0_VIEW, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280E0_CB_COLOR0_FRAG, REG_FLAG_NEED_BO, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280C0_CB_COLOR0_TILE, REG_FLAG_NEED_BO, 0, 0}, + {R_028100_CB_COLOR0_MASK, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028044_CB_COLOR1_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(1), 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280A4_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_028064_CB_COLOR1_SIZE, 0, 0, 0}, + {R_028084_CB_COLOR1_VIEW, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280E4_CB_COLOR1_FRAG, REG_FLAG_NEED_BO, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280C4_CB_COLOR1_TILE, REG_FLAG_NEED_BO, 0, 0}, + {R_028104_CB_COLOR1_MASK, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028048_CB_COLOR2_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(2), 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280A8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_028068_CB_COLOR2_SIZE, 0, 0, 0}, + {R_028088_CB_COLOR2_VIEW, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280E8_CB_COLOR2_FRAG, REG_FLAG_NEED_BO, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280C8_CB_COLOR2_TILE, REG_FLAG_NEED_BO, 0, 0}, + {R_028108_CB_COLOR2_MASK, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_02804C_CB_COLOR3_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(3), 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280AC_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_02806C_CB_COLOR3_SIZE, 0, 0, 0}, + {R_02808C_CB_COLOR3_VIEW, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280EC_CB_COLOR3_FRAG, REG_FLAG_NEED_BO, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280CC_CB_COLOR3_TILE, REG_FLAG_NEED_BO, 0, 0}, + {R_02810C_CB_COLOR3_MASK, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028050_CB_COLOR4_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(4), 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280B0_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_028070_CB_COLOR4_SIZE, 0, 0, 0}, + {R_028090_CB_COLOR4_VIEW, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280F0_CB_COLOR4_FRAG, REG_FLAG_NEED_BO, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280D0_CB_COLOR4_TILE, REG_FLAG_NEED_BO, 0, 0}, + {R_028110_CB_COLOR4_MASK, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028054_CB_COLOR5_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(5), 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280B4_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_028074_CB_COLOR5_SIZE, 0, 0, 0}, + {R_028094_CB_COLOR5_VIEW, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280F4_CB_COLOR5_FRAG, REG_FLAG_NEED_BO, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280D4_CB_COLOR5_TILE, REG_FLAG_NEED_BO, 0, 0}, + {R_028114_CB_COLOR5_MASK, 0, 0, 0}, + {R_028058_CB_COLOR6_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(6), 0}, + {R_0280B8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_028078_CB_COLOR6_SIZE, 0, 0, 0}, + {R_028098_CB_COLOR6_VIEW, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280F8_CB_COLOR6_FRAG, REG_FLAG_NEED_BO, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280D8_CB_COLOR6_TILE, REG_FLAG_NEED_BO, 0, 0}, + {R_028118_CB_COLOR6_MASK, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_02805C_CB_COLOR7_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(7), 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0280BC_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, + {R_02807C_CB_COLOR7_SIZE, 0, 0, 0}, + {R_02809C_CB_COLOR7_VIEW, 0, 0, 0}, + {R_0280FC_CB_COLOR7_FRAG, REG_FLAG_NEED_BO, 0, 0}, + {R_0280DC_CB_COLOR7_TILE, REG_FLAG_NEED_BO, 0, 0}, + {R_02811C_CB_COLOR7_MASK, 0, 0, 0}, + {R_028120_CB_CLEAR_RED, 0, 0, 0}, + {R_028124_CB_CLEAR_GREEN, 0, 0, 0}, + {R_028128_CB_CLEAR_BLUE, 0, 0, 0}, + {R_02812C_CB_CLEAR_ALPHA, 0, 0, 0}, + {R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0}, + {R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0}, + {R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {R_02823C_CB_SHADER_MASK, 0, 0, 0}, + {R_028238_CB_TARGET_MASK, 0, 0, 0}, + {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0}, + {R_028414_CB_BLEND_RED, 0, 0, 0}, + {R_028418_CB_BLEND_GREEN, 0, 0, 0}, + {R_02841C_CB_BLEND_BLUE, 0, 0, 0}, + {R_028420_CB_BLEND_ALPHA, 0, 0, 0}, + {R_028424_CB_FOG_RED, 0, 0, 0}, + {R_028428_CB_FOG_GREEN, 0, 0, 0}, + {R_02842C_CB_FOG_BLUE, 0, 0, 0}, + {R_028430_DB_STENCILREFMASK, 0, 0, 0}, + {R_028434_DB_STENCILREFMASK_BF, 0, 0, 0}, + {R_028438_SX_ALPHA_REF, 0, 0, 0}, + {R_0286DC_SPI_FOG_CNTL, 0, 0, 0}, + {R_0286E0_SPI_FOG_FUNC_SCALE, 0, 0, 0}, + {R_0286E4_SPI_FOG_FUNC_BIAS, 0, 0, 0}, + {R_028780_CB_BLEND0_CONTROL, 0, 0, 0}, + {R_028784_CB_BLEND1_CONTROL, 0, 0, 0}, + {R_028788_CB_BLEND2_CONTROL, 0, 0, 0}, + {R_02878C_CB_BLEND3_CONTROL, 0, 0, 0}, + {R_028790_CB_BLEND4_CONTROL, 0, 0, 0}, + {R_028794_CB_BLEND5_CONTROL, 0, 0, 0}, + {R_028798_CB_BLEND6_CONTROL, 0, 0, 0}, + {R_02879C_CB_BLEND7_CONTROL, 0, 0, 0}, + {R_0287A0_CB_SHADER_CONTROL, 0, 0, 0}, + {R_028800_DB_DEPTH_CONTROL, 0, 0, 0}, + {R_028804_CB_BLEND_CONTROL, 0, 0, 0}, + {R_028808_CB_COLOR_CONTROL, 0, 0, 0}, + {R_02880C_DB_SHADER_CONTROL, 0, 0, 0}, + {R_028C04_PA_SC_AA_CONFIG, 0, 0, 0}, + {R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0, 0}, + {R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, 0, 0, 0}, + {R_028C30_CB_CLRCMP_CONTROL, 0, 0, 0}, + {R_028C34_CB_CLRCMP_SRC, 0, 0, 0}, + {R_028C38_CB_CLRCMP_DST, 0, 0, 0}, + {R_028C3C_CB_CLRCMP_MSK, 0, 0, 0}, + {R_028C48_PA_SC_AA_MASK, 0, 0, 0}, + {R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0}, + {R_028D44_DB_ALPHA_TO_MASK, 0, 0, 0}, + {R_02800C_DB_DEPTH_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_DEPTH, 0}, + {R_028000_DB_DEPTH_SIZE, 0, 0, 0}, + {R_028004_DB_DEPTH_VIEW, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028010_DB_DEPTH_INFO, REG_FLAG_NEED_BO, 0, 0}, + {R_028D0C_DB_RENDER_CONTROL, 0, 0, 0}, + {R_028D10_DB_RENDER_OVERRIDE, 0, 0, 0}, + {R_028D24_DB_HTILE_SURFACE, 0, 0, 0}, + {R_028D30_DB_PRELOAD_CONTROL, 0, 0, 0}, + {R_028D34_DB_PREFETCH_LIMIT, 0, 0, 0}, + {R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0}, + {R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0}, + {R_028200_PA_SC_WINDOW_OFFSET, 0, 0, 0}, + {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0}, + {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0}, + {R_02820C_PA_SC_CLIPRECT_RULE, 0, 0, 0}, + {R_028210_PA_SC_CLIPRECT_0_TL, 0, 0, 0}, + {R_028214_PA_SC_CLIPRECT_0_BR, 0, 0, 0}, + {R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0}, + {R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0}, + {R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0}, + {R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0}, + {R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0}, + {R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0}, + {R_028230_PA_SC_EDGERULE, 0, 0, 0}, + {R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0}, + {R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0}, + {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0}, + {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0}, + {R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0}, + {R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0}, + {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0}, + {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0}, + {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0}, + {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0}, + {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0}, + {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0}, + {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0, 0}, + {R_028810_PA_CL_CLIP_CNTL, 0, 0, 0}, + {R_028814_PA_SU_SC_MODE_CNTL, 0, 0, 0}, + {R_028818_PA_CL_VTE_CNTL, 0, 0, 0}, + {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0, 0}, + {R_028820_PA_CL_NANINF_CNTL, 0, 0, 0}, + {R_028A00_PA_SU_POINT_SIZE, 0, 0, 0}, + {R_028A04_PA_SU_POINT_MINMAX, 0, 0, 0}, + {R_028A08_PA_SU_LINE_CNTL, 0, 0, 0}, + {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0, 0}, + {R_028A48_PA_SC_MPASS_PS_CNTL, 0, 0, 0}, + {R_028C00_PA_SC_LINE_CNTL, 0, 0, 0}, + {R_028C08_PA_SU_VTX_CNTL, 0, 0, 0}, + {R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0}, + {R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0}, + {R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0}, + {R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0, 0}, + {R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0, 0}, + {R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0}, + {R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0}, + {R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0}, + {R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0}, + {R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0}, + {R_028E20_PA_CL_UCP0_X, 0, 0, 0}, + {R_028E24_PA_CL_UCP0_Y, 0, 0, 0}, + {R_028E28_PA_CL_UCP0_Z, 0, 0, 0}, + {R_028E2C_PA_CL_UCP0_W, 0, 0, 0}, + {R_028E30_PA_CL_UCP1_X, 0, 0, 0}, + {R_028E34_PA_CL_UCP1_Y, 0, 0, 0}, + {R_028E38_PA_CL_UCP1_Z, 0, 0, 0}, + {R_028E3C_PA_CL_UCP1_W, 0, 0, 0}, + {R_028E40_PA_CL_UCP2_X, 0, 0, 0}, + {R_028E44_PA_CL_UCP2_Y, 0, 0, 0}, + {R_028E48_PA_CL_UCP2_Z, 0, 0, 0}, + {R_028E4C_PA_CL_UCP2_W, 0, 0, 0}, + {R_028E50_PA_CL_UCP3_X, 0, 0, 0}, + {R_028E54_PA_CL_UCP3_Y, 0, 0, 0}, + {R_028E58_PA_CL_UCP3_Z, 0, 0, 0}, + {R_028E5C_PA_CL_UCP3_W, 0, 0, 0}, + {R_028E60_PA_CL_UCP4_X, 0, 0, 0}, + {R_028E64_PA_CL_UCP4_Y, 0, 0, 0}, + {R_028E68_PA_CL_UCP4_Z, 0, 0, 0}, + {R_028E6C_PA_CL_UCP4_W, 0, 0, 0}, + {R_028E70_PA_CL_UCP5_X, 0, 0, 0}, + {R_028E74_PA_CL_UCP5_Y, 0, 0, 0}, + {R_028E78_PA_CL_UCP5_Z, 0, 0, 0}, + {R_028E7C_PA_CL_UCP5_W, 0, 0, 0}, + {R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0}, + {R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0}, + {R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0}, + {R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0}, + {R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0}, + {R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0}, + {R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0}, + {R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0}, + {R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0}, + {R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0}, + {R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0}, + {R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0}, + {R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0}, + {R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0}, + {R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0}, + {R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0}, + {R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0}, + {R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0}, + {R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0}, + {R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0}, + {R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0}, + {R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0}, + {R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0}, + {R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0}, + {R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0}, + {R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0}, + {R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0}, + {R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0}, + {R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0}, + {R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0}, + {R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0}, + {R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0}, + {R_028614_SPI_VS_OUT_ID_0, 0, 0, 0}, + {R_028618_SPI_VS_OUT_ID_1, 0, 0, 0}, + {R_02861C_SPI_VS_OUT_ID_2, 0, 0, 0}, + {R_028620_SPI_VS_OUT_ID_3, 0, 0, 0}, + {R_028624_SPI_VS_OUT_ID_4, 0, 0, 0}, + {R_028628_SPI_VS_OUT_ID_5, 0, 0, 0}, + {R_02862C_SPI_VS_OUT_ID_6, 0, 0, 0}, + {R_028630_SPI_VS_OUT_ID_7, 0, 0, 0}, + {R_028634_SPI_VS_OUT_ID_8, 0, 0, 0}, + {R_028638_SPI_VS_OUT_ID_9, 0, 0, 0}, + {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028858_SQ_PGM_START_VS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028868_SQ_PGM_RESOURCES_VS, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028894_SQ_PGM_START_FS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0, 0}, + {R_0288D0_SQ_PGM_CF_OFFSET_VS, 0, 0, 0}, + {R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0, 0}, + {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0}, + {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0}, + {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0}, + {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0}, + {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0}, + {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0}, + {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0}, + {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0}, + {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0}, + {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0}, + {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0}, + {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0}, + {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0}, + {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0}, + {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0}, + {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0}, + {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0}, + {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0}, + {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0}, + {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0}, + {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0}, + {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0}, + {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0}, + {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0}, + {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0}, + {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0}, + {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0}, + {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0}, + {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0}, + {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0}, + {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0}, + {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0}, + {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0}, + {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0, 0}, + {R_0286D8_SPI_INPUT_Z, 0, 0, 0}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, + {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, + {R_028850_SQ_PGM_RESOURCES_PS, 0, 0, 0}, + {R_028854_SQ_PGM_EXPORTS_PS, 0, 0, 0}, + {R_0288CC_SQ_PGM_CF_OFFSET_PS, 0, 0, 0}, + {R_028400_VGT_MAX_VTX_INDX, 0, 0, 0}, + {R_028404_VGT_MIN_VTX_INDX, 0, 0, 0}, + {R_028408_VGT_INDX_OFFSET, 0, 0, 0}, + {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0}, + {R_028A84_VGT_PRIMITIVEID_EN, 0, 0, 0}, + {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0, 0}, + {R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0, 0, 0}, + {R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0, 0, 0}, }; /* SHADER RESOURCE R600/R700 */ static int r600_state_resource_init(struct r600_context *ctx, u32 offset) { struct r600_reg r600_shader_resource[] = { - {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038000_RESOURCE0_WORD0, 0, 0, 0}, - {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038004_RESOURCE0_WORD1, 0, 0, 0}, - {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038008_RESOURCE0_WORD2, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF}, - {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_03800C_RESOURCE0_WORD3, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF}, - {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038010_RESOURCE0_WORD4, 0, 0, 0}, - {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038014_RESOURCE0_WORD5, 0, 0, 0}, - {PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038018_RESOURCE0_WORD6, 0, 0, 0}, + {R_038000_RESOURCE0_WORD0, 0, 0, 0}, + {R_038004_RESOURCE0_WORD1, 0, 0, 0}, + {R_038008_RESOURCE0_WORD2, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF}, + {R_03800C_RESOURCE0_WORD3, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF}, + {R_038010_RESOURCE0_WORD4, 0, 0, 0}, + {R_038014_RESOURCE0_WORD5, 0, 0, 0}, + {R_038018_RESOURCE0_WORD6, 0, 0, 0}, }; unsigned nreg = Elements(r600_shader_resource); for (int i = 0; i < nreg; i++) { r600_shader_resource[i].offset += offset; } - return r600_context_add_block(ctx, r600_shader_resource, nreg); + return r600_context_add_block(ctx, r600_shader_resource, nreg, PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET); } /* SHADER SAMPLER R600/R700 */ static int r600_state_sampler_init(struct r600_context *ctx, u32 offset) { struct r600_reg r600_shader_sampler[] = { - {PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET, R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0}, - {PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET, R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0, 0}, - {PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET, R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0, 0}, + {R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0}, + {R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0, 0}, + {R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0, 0}, }; unsigned nreg = Elements(r600_shader_sampler); for (int i = 0; i < nreg; i++) { r600_shader_sampler[i].offset += offset; } - return r600_context_add_block(ctx, r600_shader_sampler, nreg); + return r600_context_add_block(ctx, r600_shader_sampler, nreg, PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET); } /* SHADER SAMPLER BORDER R600/R700 */ static int r600_state_sampler_border_init(struct r600_context *ctx, u32 offset) { struct r600_reg r600_shader_sampler_border[] = { - {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A400_TD_PS_SAMPLER0_BORDER_RED, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0, 0}, - {PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0, 0}, + {R_00A400_TD_PS_SAMPLER0_BORDER_RED, 0, 0, 0}, + {R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0, 0}, + {R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0, 0}, + {R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0, 0}, }; unsigned nreg = Elements(r600_shader_sampler_border); for (int i = 0; i < nreg; i++) { r600_shader_sampler_border[i].offset += offset; } - return r600_context_add_block(ctx, r600_shader_sampler_border, nreg); + return r600_context_add_block(ctx, r600_shader_sampler_border, nreg, PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET); } static int r600_loop_const_init(struct r600_context *ctx, u32 offset) @@ -585,14 +592,12 @@ static int r600_loop_const_init(struct r600_context *ctx, u32 offset) int i; for (i = 0; i < nreg; i++) { - r600_loop_consts[i].opcode = PKT3_SET_LOOP_CONST; - r600_loop_consts[i].offset_base = R600_LOOP_CONST_OFFSET; r600_loop_consts[i].offset = R600_LOOP_CONST_OFFSET + ((offset + i) * 4); r600_loop_consts[i].flags = REG_FLAG_DIRTY_ALWAYS; r600_loop_consts[i].flush_flags = 0; r600_loop_consts[i].flush_mask = 0; } - return r600_context_add_block(ctx, r600_loop_consts, nreg); + return r600_context_add_block(ctx, r600_loop_consts, nreg, PKT3_SET_LOOP_CONST, R600_LOOP_CONST_OFFSET); } static void r600_context_clear_fenced_bo(struct r600_context *ctx) @@ -612,8 +617,10 @@ void r600_context_fini(struct r600_context *ctx) struct r600_block *block; struct r600_range *range; - for (int i = 0; i < 256; i++) { - for (int j = 0; j < (1 << ctx->hash_shift); j++) { + for (int i = 0; i < NUM_RANGES; i++) { + if (!ctx->range[i].blocks) + continue; + for (int j = 0; j < (1 << HASH_SHIFT); j++) { block = ctx->range[i].blocks[j]; if (block) { for (int k = 0, offset = block->start_offset; k < block->nreg; k++, offset += 4) { @@ -628,6 +635,7 @@ void r600_context_fini(struct r600_context *ctx) } free(ctx->range[i].blocks); } + free(ctx->range); free(ctx->blocks); free(ctx->reloc); free(ctx->bo); @@ -637,6 +645,36 @@ void r600_context_fini(struct r600_context *ctx) memset(ctx, 0, sizeof(struct r600_context)); } +int r600_setup_block_table(struct r600_context *ctx) +{ + /* setup block table */ + ctx->blocks = calloc(ctx->nblocks, sizeof(void*)); + if (!ctx->blocks) + return -ENOMEM; + for (int i = 0, c = 0; i < NUM_RANGES; i++) { + if (!ctx->range[i].blocks) + continue; + for (int j = 0, add; j < (1 << HASH_SHIFT); j++) { + if (!ctx->range[i].blocks[j]) + continue; + + add = 1; + for (int k = 0; k < c; k++) { + if (ctx->blocks[k] == ctx->range[i].blocks[j]) { + add = 0; + break; + } + } + if (add) { + assert(c < ctx->nblocks); + ctx->blocks[c++] = ctx->range[i].blocks[j]; + j += (ctx->range[i].blocks[j]->nreg) - 1; + } + } + } + return 0; +} + int r600_context_init(struct r600_context *ctx, struct radeon *radeon) { int r; @@ -645,30 +683,23 @@ int r600_context_init(struct r600_context *ctx, struct radeon *radeon) ctx->radeon = radeon; LIST_INITHEAD(&ctx->query_list); - /* initialize hash */ - ctx->hash_size = 19; - ctx->hash_shift = 11; - for (int i = 0; i < 256; i++) { - ctx->range[i].start_offset = i << ctx->hash_shift; - ctx->range[i].end_offset = ((i + 1) << ctx->hash_shift) - 1; - ctx->range[i].blocks = calloc(1 << ctx->hash_shift, sizeof(void*)); - if (ctx->range[i].blocks == NULL) { - r = -ENOMEM; - goto out_err; - } + ctx->range = calloc(NUM_RANGES, sizeof(struct r600_range)); + if (!ctx->range) { + r = -ENOMEM; + goto out_err; } /* add blocks */ r = r600_context_add_block(ctx, r600_config_reg_list, - Elements(r600_config_reg_list)); + Elements(r600_config_reg_list), PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET); if (r) goto out_err; r = r600_context_add_block(ctx, r600_context_reg_list, - Elements(r600_context_reg_list)); + Elements(r600_context_reg_list), PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET); if (r) goto out_err; r = r600_context_add_block(ctx, r600_ctl_const_list, - Elements(r600_ctl_const_list)); + Elements(r600_ctl_const_list), PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET); if (r) goto out_err; @@ -721,26 +752,9 @@ int r600_context_init(struct r600_context *ctx, struct radeon *radeon) /* VS loop const */ r600_loop_const_init(ctx, 32); - /* setup block table */ - ctx->blocks = calloc(ctx->nblocks, sizeof(void*)); - for (int i = 0, c = 0; i < 256; i++) { - for (int j = 0, add; j < (1 << ctx->hash_shift); j++) { - if (ctx->range[i].blocks[j]) { - add = 1; - for (int k = 0; k < c; k++) { - if (ctx->blocks[k] == ctx->range[i].blocks[j]) { - add = 0; - break; - } - } - if (add) { - assert(c < ctx->nblocks); - ctx->blocks[c++] = ctx->range[i].blocks[j]; - j += (ctx->range[i].blocks[j]->nreg << 2) - 1; - } - } - } - } + r = r600_setup_block_table(ctx); + if (r) + goto out_err; /* allocate cs variables */ ctx->nreloc = RADEON_CTX_MAX_PM4; @@ -810,12 +824,17 @@ void r600_context_bo_flush(struct r600_context *ctx, unsigned flush_flags, G_0085F0_DB_ACTION_ENA(flush_flags))) { if (ctx->flags & R600_CONTEXT_CHECK_EVENT_FLUSH) { /* the rv670 seems to fail fbo-generatemipmap unless we flush the CB1 dest base ena */ - if (ctx->radeon->family == CHIP_RV670) { - ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, ctx->predicate_drawing); - ctx->pm4[ctx->pm4_cdwords++] = S_0085F0_CB1_DEST_BASE_ENA(1); /* CP_COHER_CNTL */ - ctx->pm4[ctx->pm4_cdwords++] = 0xffffffff; /* CP_COHER_SIZE */ - ctx->pm4[ctx->pm4_cdwords++] = 0; /* CP_COHER_BASE */ - ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A; /* POLL_INTERVAL */ + if ((bo->binding & BO_BOUND_TEXTURE) && + (flush_flags & S_0085F0_CB_ACTION_ENA(1))) { + if ((ctx->radeon->family == CHIP_RV670) || + (ctx->radeon->family == CHIP_RS780) || + (ctx->radeon->family == CHIP_RS880)) { + ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, ctx->predicate_drawing); + ctx->pm4[ctx->pm4_cdwords++] = S_0085F0_CB1_DEST_BASE_ENA(1); /* CP_COHER_CNTL */ + ctx->pm4[ctx->pm4_cdwords++] = 0xffffffff; /* CP_COHER_SIZE */ + ctx->pm4[ctx->pm4_cdwords++] = 0; /* CP_COHER_BASE */ + ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A; /* POLL_INTERVAL */ + } } ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, ctx->predicate_drawing); @@ -906,16 +925,17 @@ void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_stat int dirty; for (int i = 0; i < state->nregs; i++) { unsigned id, reloc_id; + struct r600_pipe_reg *reg = &state->regs[i]; - range = &ctx->range[CTX_RANGE_ID(ctx, state->regs[i].offset)]; - block = range->blocks[CTX_BLOCK_ID(ctx, state->regs[i].offset)]; - id = (state->regs[i].offset - block->start_offset) >> 2; + range = &ctx->range[CTX_RANGE_ID(ctx, reg->offset)]; + block = range->blocks[CTX_BLOCK_ID(ctx, reg->offset)]; + id = (reg->offset - block->start_offset) >> 2; dirty = block->status & R600_BLOCK_STATUS_DIRTY; new_val = block->reg[id]; - new_val &= ~state->regs[i].mask; - new_val |= state->regs[i].value; + new_val &= ~reg->mask; + new_val |= reg->value; if (new_val != block->reg[id]) { block->reg[id] = new_val; dirty |= R600_BLOCK_STATUS_DIRTY; @@ -925,8 +945,8 @@ void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_stat if (block->pm4_bo_index[id] && state->regs[i].bo) { /* find relocation */ reloc_id = block->pm4_bo_index[id]; - r600_bo_reference(ctx->radeon, &block->reloc[reloc_id].bo, state->regs[i].bo); - state->regs[i].bo->fence = ctx->radeon->fence; + r600_bo_reference(ctx->radeon, &block->reloc[reloc_id].bo, reg->bo); + reg->bo->fence = ctx->radeon->fence; /* always force dirty for relocs for now */ dirty |= R600_BLOCK_STATUS_DIRTY; } @@ -947,6 +967,9 @@ void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_ block = range->blocks[CTX_BLOCK_ID(ctx, offset)]; if (state == NULL) { block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY); + if (block->reloc[1].bo) + block->reloc[1].bo->bo->binding &= ~BO_BOUND_TEXTURE; + r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL); r600_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL); LIST_DELINIT(&block->list); @@ -1000,6 +1023,7 @@ void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_ r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[3].bo); state->regs[2].bo->fence = ctx->radeon->fence; state->regs[3].bo->fence = ctx->radeon->fence; + state->regs[2].bo->bo->binding |= BO_BOUND_TEXTURE; } } r600_context_dirty_block(ctx, block, dirty, num_regs - 1); diff --git a/src/gallium/winsys/r600/drm/r600_priv.h b/src/gallium/winsys/r600/drm/r600_priv.h index f8363f9272b..4f7e60c3413 100644 --- a/src/gallium/winsys/r600/drm/r600_priv.h +++ b/src/gallium/winsys/r600/drm/r600_priv.h @@ -67,14 +67,13 @@ struct radeon { #define REG_FLAG_RV6XX_SBU 4 struct r600_reg { - unsigned opcode; - unsigned offset_base; unsigned offset; unsigned flags; unsigned flush_flags; unsigned flush_mask; }; +#define BO_BOUND_TEXTURE 1 struct radeon_bo { struct pipe_reference reference; unsigned handle; @@ -90,6 +89,7 @@ struct radeon_bo { unsigned reloc_id; unsigned last_flush; unsigned name; + unsigned binding; }; struct r600_bo { @@ -145,6 +145,7 @@ int radeon_bo_get_tiling_flags(struct radeon *radeon, int radeon_bo_get_name(struct radeon *radeon, struct radeon_bo *bo, uint32_t *name); +int radeon_bo_fixed_map(struct radeon *radeon, struct radeon_bo *bo); /* * r600_hw_context.c @@ -154,12 +155,13 @@ void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct r600_bo *r void r600_context_bo_flush(struct r600_context *ctx, unsigned flush_flags, unsigned flush_mask, struct r600_bo *rbo); struct r600_bo *r600_context_reg_bo(struct r600_context *ctx, unsigned offset); -int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg); +int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg, + unsigned opcode, unsigned offset_base); void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset); void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block); void r600_context_dirty_block(struct r600_context *ctx, struct r600_block *block, int dirty, int index); - +int r600_setup_block_table(struct r600_context *ctx); void r600_context_reg(struct r600_context *ctx, unsigned offset, unsigned value, unsigned mask); @@ -184,14 +186,25 @@ struct r600_bo *r600_bomgr_bo_create(struct r600_bomgr *mgr, /* * helpers */ -#define CTX_RANGE_ID(ctx, offset) (((offset) >> (ctx)->hash_shift) & 255) -#define CTX_BLOCK_ID(ctx, offset) ((offset) & ((1 << (ctx)->hash_shift) - 1)) + +/* each range covers 9 bits of dword space = 512 dwords = 2k bytes */ +/* there is a block entry for each register so 512 blocks */ +/* we have no registers to read/write below 0x8000 (0x2000 in dw space) */ +/* we use some fake offsets at 0x40000 to do evergreen sampler borders so take 0x42000 as a max bound*/ +#define RANGE_OFFSET_START 0x8000 +#define HASH_SHIFT 9 +#define NUM_RANGES (0x42000 - RANGE_OFFSET_START) / (4 << HASH_SHIFT) /* 128 << 9 = 64k */ + +#define CTX_RANGE_ID(ctx, offset) ((((offset - RANGE_OFFSET_START) >> 2) >> HASH_SHIFT) & 255) +#define CTX_BLOCK_ID(ctx, offset) (((offset - RANGE_OFFSET_START) >> 2) & ((1 << HASH_SHIFT) - 1)) /* * radeon_bo.c */ static inline int radeon_bo_map(struct radeon *radeon, struct radeon_bo *bo) { + if (bo->map_count == 0 && !bo->data) + return radeon_bo_fixed_map(radeon, bo); bo->map_count++; return 0; } diff --git a/src/gallium/winsys/r600/drm/radeon_bo.c b/src/gallium/winsys/r600/drm/radeon_bo.c index 13b1d50b6e5..cd817fc240b 100644 --- a/src/gallium/winsys/r600/drm/radeon_bo.c +++ b/src/gallium/winsys/r600/drm/radeon_bo.c @@ -33,7 +33,7 @@ #include "xf86drm.h" #include "radeon_drm.h" -static int radeon_bo_fixed_map(struct radeon *radeon, struct radeon_bo *bo) +int radeon_bo_fixed_map(struct radeon *radeon, struct radeon_bo *bo) { struct drm_radeon_gem_mmap args; void *ptr; @@ -64,8 +64,10 @@ static int radeon_bo_fixed_map(struct radeon *radeon, struct radeon_bo *bo) static void radeon_bo_fixed_unmap(struct radeon *radeon, struct radeon_bo *bo) { - munmap(bo->data, bo->size); - bo->data = NULL; + if (bo->data) { + munmap(bo->data, bo->size); + bo->data = NULL; + } } struct radeon_bo *radeon_bo(struct radeon *radeon, unsigned handle, @@ -127,11 +129,6 @@ struct radeon_bo *radeon_bo(struct radeon *radeon, unsigned handle, return NULL; } } - if (radeon_bo_fixed_map(radeon, bo)) { - R600_ERR("failed to map bo\n"); - radeon_bo_reference(radeon, &bo, NULL); - return bo; - } if (handle) util_hash_table_set(radeon->bo_handles, (void *)(uintptr_t)handle, bo); diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c index 37f6d18689d..3ac57d25b5e 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c @@ -48,22 +48,59 @@ #define RADEON_INFO_WANT_CMASK 8 #endif -/* Enable/disable feature access. Return TRUE on success. */ -static boolean radeon_set_fd_access(int fd, unsigned request, boolean enable) +/* Enable/disable feature access for one command stream. + * If enable == TRUE, return TRUE on success. + * Otherwise, return FALSE. + * + * We basically do the same thing kernel does, because we have to deal + * with multiple contexts (here command streams) backed by one winsys. */ +static boolean radeon_set_fd_access(struct radeon_drm_cs *applier, + struct radeon_drm_cs **owner, + pipe_mutex *mutex, + unsigned request, boolean enable) { struct drm_radeon_info info = {0}; unsigned value = enable ? 1 : 0; + pipe_mutex_lock(*mutex); + + /* Early exit if we are sure the request will fail. */ + if (enable) { + if (*owner) { + pipe_mutex_unlock(*mutex); + return FALSE; + } + } else { + if (*owner != applier) { + pipe_mutex_unlock(*mutex); + return FALSE; + } + } + + /* Pass through the request to the kernel. */ info.value = (unsigned long)&value; info.request = request; - - if (drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info)) != 0) + if (drmCommandWriteRead(applier->ws->fd, DRM_RADEON_INFO, + &info, sizeof(info)) != 0) { + pipe_mutex_unlock(*mutex); return FALSE; + } - if (enable && !value) - return FALSE; + /* Update the rights in the winsys. */ + if (enable) { + if (value) { + *owner = applier; + fprintf(stderr, "radeon: Acquired Hyper-Z.\n"); + pipe_mutex_unlock(*mutex); + return TRUE; + } + } else { + *owner = NULL; + fprintf(stderr, "radeon: Released Hyper-Z.\n"); + } - return TRUE; + pipe_mutex_unlock(*mutex); + return FALSE; } /* Helper function to do the ioctls needed for setup and init. */ @@ -138,16 +175,6 @@ static void do_ioctls(struct radeon_drm_winsys *winsys) } winsys->z_pipes = target; - if (debug_get_bool_option("RADEON_HYPERZ", FALSE)) { - winsys->hyperz = radeon_set_fd_access(winsys->fd, - RADEON_INFO_WANT_HYPERZ, TRUE); - } - - if (debug_get_bool_option("RADEON_CMASK", FALSE)) { - winsys->aacompress = radeon_set_fd_access(winsys->fd, - RADEON_INFO_WANT_CMASK, TRUE); - } - retval = drmCommandWriteRead(winsys->fd, DRM_RADEON_GEM_INFO, &gem_info, sizeof(gem_info)); if (retval) { @@ -167,6 +194,9 @@ static void radeon_winsys_destroy(struct radeon_winsys *rws) { struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws; + pipe_mutex_destroy(ws->hyperz_owner_mutex); + pipe_mutex_destroy(ws->cmask_owner_mutex); + ws->cman->destroy(ws->cman); ws->kman->destroy(ws->kman); FREE(rws); @@ -198,14 +228,38 @@ static uint32_t radeon_get_value(struct radeon_winsys *rws, return ws->drm_major*100 + ws->drm_minor >= 206; case RADEON_VID_DRM_2_8_0: return ws->drm_major*100 + ws->drm_minor >= 208; - case RADEON_VID_CAN_HYPERZ: - return ws->hyperz; - case RADEON_VID_CAN_AACOMPRESS: - return ws->aacompress; } return 0; } +static boolean radeon_cs_request_feature(struct radeon_winsys_cs *rcs, + enum radeon_feature_id fid, + boolean enable) +{ + struct radeon_drm_cs *cs = radeon_drm_cs(rcs); + + switch (fid) { + case RADEON_FID_HYPERZ_RAM_ACCESS: + if (debug_get_bool_option("RADEON_HYPERZ", FALSE)) { + return radeon_set_fd_access(cs, &cs->ws->hyperz_owner, + &cs->ws->hyperz_owner_mutex, + RADEON_INFO_WANT_HYPERZ, enable); + } else { + return FALSE; + } + + case RADEON_FID_CMASK_RAM_ACCESS: + if (debug_get_bool_option("RADEON_CMASK", FALSE)) { + return radeon_set_fd_access(cs, &cs->ws->cmask_owner, + &cs->ws->cmask_owner_mutex, + RADEON_INFO_WANT_CMASK, enable); + } else { + return FALSE; + } + } + return FALSE; +} + struct radeon_winsys *radeon_drm_winsys_create(int fd) { struct radeon_drm_winsys *ws = CALLOC_STRUCT(radeon_drm_winsys); @@ -231,10 +285,14 @@ struct radeon_winsys *radeon_drm_winsys_create(int fd) /* Set functions. */ ws->base.destroy = radeon_winsys_destroy; ws->base.get_value = radeon_get_value; + ws->base.cs_request_feature = radeon_cs_request_feature; radeon_bomgr_init_functions(ws); radeon_drm_cs_init_functions(ws); + pipe_mutex_init(ws->hyperz_owner_mutex); + pipe_mutex_init(ws->cmask_owner_mutex); + return &ws->base; fail: diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h index e1b9493fc10..d5186bc4d17 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h @@ -32,6 +32,8 @@ #include "radeon_winsys.h" +#include "os/os_thread.h" + struct radeon_drm_winsys { struct radeon_winsys base; @@ -52,10 +54,10 @@ struct radeon_drm_winsys { unsigned drm_minor; unsigned drm_patchlevel; - /* Hyper-Z user */ - boolean hyperz; - /* AA compression (CMask) */ - boolean aacompress; + struct radeon_drm_cs *hyperz_owner; + pipe_mutex hyperz_owner_mutex; + struct radeon_drm_cs *cmask_owner; + pipe_mutex cmask_owner_mutex; }; static INLINE struct radeon_drm_winsys * diff --git a/src/gallium/winsys/radeon/drm/radeon_winsys.h b/src/gallium/winsys/radeon/drm/radeon_winsys.h index ca0e6624138..3a64e4abc35 100644 --- a/src/gallium/winsys/radeon/drm/radeon_winsys.h +++ b/src/gallium/winsys/radeon/drm/radeon_winsys.h @@ -87,9 +87,11 @@ enum radeon_value_id { * - TBD */ RADEON_VID_DRM_2_8_0, +}; - RADEON_VID_CAN_HYPERZ, /* ZMask + HiZ */ - RADEON_VID_CAN_AACOMPRESS, /* CMask */ +enum radeon_feature_id { + RADEON_FID_HYPERZ_RAM_ACCESS, /* ZMask + HiZ */ + RADEON_FID_CMASK_RAM_ACCESS, }; struct radeon_winsys { @@ -314,6 +316,16 @@ struct radeon_winsys { */ boolean (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs, struct radeon_winsys_cs_handle *buf); + + /** + * Request access to a feature for a command stream. + * + * \param cs A command stream. + * \param fid A winsys buffer. + */ + boolean (*cs_request_feature)(struct radeon_winsys_cs *cs, + enum radeon_feature_id fid, + boolean enable); }; #endif diff --git a/src/gallium/winsys/svga/drm/vmw_screen_svga.c b/src/gallium/winsys/svga/drm/vmw_screen_svga.c index d96b2b97427..c362aa39938 100644 --- a/src/gallium/winsys/svga/drm/vmw_screen_svga.c +++ b/src/gallium/winsys/svga/drm/vmw_screen_svga.c @@ -201,6 +201,19 @@ vmw_svga_winsys_destroy(struct svga_winsys_screen *sws) } +static SVGA3dHardwareVersion +vmw_svga_winsys_get_hw_version(struct svga_winsys_screen *sws) +{ + struct vmw_winsys_screen *vws = vmw_winsys_screen(sws); + + if (!vws->ioctl.fifo_map) { + return 0; + } + + return vws->ioctl.fifo_map[SVGA_FIFO_3D_HWVERSION]; +} + + static boolean vmw_svga_winsys_get_cap(struct svga_winsys_screen *sws, SVGA3dDevCapIndex index, @@ -276,6 +289,7 @@ boolean vmw_winsys_screen_init_svga(struct vmw_winsys_screen *vws) { vws->base.destroy = vmw_svga_winsys_destroy; + vws->base.get_hw_version = vmw_svga_winsys_get_hw_version; vws->base.get_cap = vmw_svga_winsys_get_cap; vws->base.context_create = vmw_svga_winsys_context_create; vws->base.surface_create = vmw_svga_winsys_surface_create; diff --git a/src/glsl/builtins/profiles/ARB_shader_texture_lod.frag b/src/glsl/builtins/profiles/ARB_shader_texture_lod.frag new file mode 100644 index 00000000000..c15e2a10a5b --- /dev/null +++ b/src/glsl/builtins/profiles/ARB_shader_texture_lod.frag @@ -0,0 +1,64 @@ +/* + * The existing isotropic vertex texture functions are added to the + * built-in functions for fragment shaders. + */ +vec4 texture1DLod (sampler1D sampler, float coord, float lod); +vec4 texture1DProjLod(sampler1D sampler, vec2 coord, float lod); +vec4 texture1DProjLod(sampler1D sampler, vec4 coord, float lod); +vec4 texture2DLod (sampler2D sampler, vec2 coord, float lod); +vec4 texture2DProjLod(sampler2D sampler, vec3 coord, float lod); +vec4 texture2DProjLod(sampler2D sampler, vec4 coord, float lod); +vec4 texture3DLod (sampler3D sampler, vec3 coord, float lod); +vec4 texture3DProjLod(sampler3D sampler, vec4 coord, float lod); +vec4 textureCubeLod (samplerCube sampler, vec3 coord, float lod); +vec4 shadow1DLod (sampler1DShadow sampler, vec3 coord, float lod); +vec4 shadow2DLod (sampler2DShadow sampler, vec3 coord, float lod); +vec4 shadow1DProjLod(sampler1DShadow sampler, vec4 coord, float lod); +vec4 shadow2DProjLod(sampler2DShadow sampler, vec4 coord, float lod); + +/* New anisotropic texture functions, providing explicit derivatives: */ +vec4 texture1DGradARB (sampler1D sampler, + float P, float dPdx, float dPdy); +vec4 texture1DProjGradARB (sampler1D sampler, + vec2 P, float dPdx, float dPdy); +vec4 texture1DProjGradARB (sampler1D sampler, + vec4 P, float dPdx, float dPdy); + +vec4 texture2DGradARB (sampler2D sampler, + vec2 P, vec2 dPdx, vec2 dPdy); +vec4 texture2DProjGradARB (sampler2D sampler, + vec3 P, vec2 dPdx, vec2 dPdy); +vec4 texture2DProjGradARB (sampler2D sampler, + vec4 P, vec2 dPdx, vec2 dPdy); + +vec4 texture3DGradARB (sampler3D sampler, + vec3 P, vec3 dPdx, vec3 dPdy); +vec4 texture3DProjGradARB (sampler3D sampler, + vec4 P, vec3 dPdx, vec3 dPdy); + +vec4 textureCubeGradARB (samplerCube sampler, + vec3 P, vec3 dPdx, vec3 dPdy); + +vec4 shadow1DGradARB (sampler1DShadow sampler, + vec3 P, float dPdx, float dPdy); +vec4 shadow1DProjGradARB (sampler1DShadow sampler, + vec4 P, float dPdx, float dPdy); + +vec4 shadow2DGradARB (sampler2DShadow sampler, + vec3 P, vec2 dPdx, vec2 dPdy); +vec4 shadow2DProjGradARB (sampler2DShadow sampler, + vec4 P, vec2 dPdx, vec2 dPdy); + +#ifdef GL_ARB_texture_rectangle +vec4 texture2DRectGradARB (sampler2DRect sampler, + vec2 P, vec2 dPdx, vec2 dPdy); +vec4 texture2DRectProjGradARB(sampler2DRect sampler, + vec3 P, vec2 dPdx, vec2 dPdy); +vec4 texture2DRectProjGradARB(sampler2DRect sampler, + vec4 P, vec2 dPdx, vec2 dPdy); + +vec4 shadow2DRectGradARB (sampler2DRectShadow sampler, + vec3 P, vec2 dPdx, vec2 dPdy); +vec4 shadow2DRectProjGradARB (sampler2DRectShadow sampler, + vec4 P, vec2 dPdx, vec2 dPdy); +#endif diff --git a/src/glsl/builtins/profiles/ARB_shader_texture_lod.vert b/src/glsl/builtins/profiles/ARB_shader_texture_lod.vert new file mode 100644 index 00000000000..edfed26fc98 --- /dev/null +++ b/src/glsl/builtins/profiles/ARB_shader_texture_lod.vert @@ -0,0 +1,46 @@ +/* New anisotropic texture functions, providing explicit derivatives: */ +vec4 texture1DGradARB (sampler1D sampler, + float P, float dPdx, float dPdy); +vec4 texture1DProjGradARB (sampler1D sampler, + vec2 P, float dPdx, float dPdy); +vec4 texture1DProjGradARB (sampler1D sampler, + vec4 P, float dPdx, float dPdy); + +vec4 texture2DGradARB (sampler2D sampler, + vec2 P, vec2 dPdx, vec2 dPdy); +vec4 texture2DProjGradARB (sampler2D sampler, + vec3 P, vec2 dPdx, vec2 dPdy); +vec4 texture2DProjGradARB (sampler2D sampler, + vec4 P, vec2 dPdx, vec2 dPdy); + +vec4 texture3DGradARB (sampler3D sampler, + vec3 P, vec3 dPdx, vec3 dPdy); +vec4 texture3DProjGradARB (sampler3D sampler, + vec4 P, vec3 dPdx, vec3 dPdy); + +vec4 textureCubeGradARB (samplerCube sampler, + vec3 P, vec3 dPdx, vec3 dPdy); + +vec4 shadow1DGradARB (sampler1DShadow sampler, + vec3 P, float dPdx, float dPdy); +vec4 shadow1DProjGradARB (sampler1DShadow sampler, + vec4 P, float dPdx, float dPdy); + +vec4 shadow2DGradARB (sampler2DShadow sampler, + vec3 P, vec2 dPdx, vec2 dPdy); +vec4 shadow2DProjGradARB (sampler2DShadow sampler, + vec4 P, vec2 dPdx, vec2 dPdy); + +#ifdef GL_ARB_texture_rectangle +vec4 texture2DRectGradARB (sampler2DRect sampler, + vec2 P, vec2 dPdx, vec2 dPdy); +vec4 texture2DRectProjGradARB(sampler2DRect sampler, + vec3 P, vec2 dPdx, vec2 dPdy); +vec4 texture2DRectProjGradARB(sampler2DRect sampler, + vec4 P, vec2 dPdx, vec2 dPdy); + +vec4 shadow2DRectGradARB (sampler2DRectShadow sampler, + vec3 P, vec2 dPdx, vec2 dPdy); +vec4 shadow2DRectProjGradARB (sampler2DRectShadow sampler, + vec4 P, vec2 dPdx, vec2 dPdy); +#endif diff --git a/src/glsl/builtins/tools/texture_builtins.py b/src/glsl/builtins/tools/texture_builtins.py index 2fbe79010f9..a4054caac98 100755 --- a/src/glsl/builtins/tools/texture_builtins.py +++ b/src/glsl/builtins/tools/texture_builtins.py @@ -369,6 +369,70 @@ def generate_texture_functions(fs): generate_sigs("", "tex", "2DArrayShadow") end_function(fs, "shadow2DArray") + # ARB_shader_texture_lod extension + start_function("texture1DGradARB") + generate_fiu_sigs("txd", "1D") + end_function(fs, "texture1DGradARB") + + start_function("texture2DGradARB") + generate_fiu_sigs("txd", "2D") + end_function(fs, "texture2DGradARB") + + start_function("texture3DGradARB") + generate_fiu_sigs("txd", "3D") + end_function(fs, "texture3DGradARB") + + start_function("textureCubeGradARB") + generate_fiu_sigs("txd", "Cube") + end_function(fs, "textureCubeGradARB") + + start_function("texture1DProjGradARB") + generate_fiu_sigs("txd", "1D", True) + generate_fiu_sigs("txd", "1D", True, 2) + end_function(fs, "texture1DProjGradARB") + + start_function("texture2DProjGradARB") + generate_fiu_sigs("txd", "2D", True) + generate_fiu_sigs("txd", "2D", True, 1) + end_function(fs, "texture2DProjGradARB") + + start_function("texture3DProjGradARB") + generate_fiu_sigs("txd", "3D", True) + end_function(fs, "texture3DProjGradARB") + + start_function("shadow1DGradARB") + generate_sigs("", "txd", "1DShadow", False, 1) + end_function(fs, "shadow1DGradARB") + + start_function("shadow1DProjGradARB") + generate_sigs("", "txd", "1DShadow", True, 1) + end_function(fs, "shadow1DProjGradARB") + + start_function("shadow2DGradARB") + generate_sigs("", "txd", "2DShadow", False) + end_function(fs, "shadow2DGradARB") + + start_function("shadow2DProjGradARB") + generate_sigs("", "txd", "2DShadow", True) + end_function(fs, "shadow2DProjGradARB") + + start_function("texture2DRectGradARB") + generate_sigs("", "txd", "2DRect") + end_function(fs, "texture2DRectGradARB") + + start_function("texture2DRectProjGradARB") + generate_sigs("", "txd", "2DRect", True) + generate_sigs("", "txd", "2DRect", True, 1) + end_function(fs, "texture2DRectProjGradARB") + + start_function("shadow2DRectGradARB") + generate_sigs("", "txd", "2DRectShadow", False) + end_function(fs, "shadow2DRectGradARB") + + start_function("shadow2DRectProjGradARB") + generate_sigs("", "txd", "2DRectShadow", True) + end_function(fs, "shadow2DRectProjGradARB") + # Deprecated (110/120 style) functions with silly names: start_function("texture1D") generate_sigs("", "tex", "1D") diff --git a/src/glsl/glcpp/glcpp-parse.y b/src/glsl/glcpp/glcpp-parse.y index 6f15e85a122..0a35e88cec7 100644 --- a/src/glsl/glcpp/glcpp-parse.y +++ b/src/glsl/glcpp/glcpp-parse.y @@ -1128,6 +1128,10 @@ glcpp_parser_create (const struct gl_extensions *extensions, int api) if (extensions->ARB_explicit_attrib_location) add_builtin_define(parser, "GL_ARB_explicit_attrib_location", 1); + + if (extensions->ARB_shader_texture_lod) + add_builtin_define(parser, "GL_ARB_shader_texture_lod", 1); + if (extensions->AMD_conservative_depth) add_builtin_define(parser, "GL_AMD_conservative_depth", 1); } diff --git a/src/glsl/glsl_parser_extras.cpp b/src/glsl/glsl_parser_extras.cpp index 18bff88deec..fce2faa758b 100644 --- a/src/glsl/glsl_parser_extras.cpp +++ b/src/glsl/glsl_parser_extras.cpp @@ -240,6 +240,14 @@ _mesa_glsl_process_extension(const char *name, YYLTYPE *name_locp, state->EXT_texture_array_warn = (ext_mode == extension_warn); unsupported = !state->extensions->EXT_texture_array; + } else if (strcmp(name, "GL_ARB_shader_texture_lod") == 0) { + /* Force ARB_texture_rectangle to be on so sampler2DRects are defined */ + state->ARB_texture_rectangle_enable = true; + + state->ARB_shader_texture_lod_enable = (ext_mode != extension_disable); + state->ARB_shader_texture_lod_warn = (ext_mode == extension_warn); + + unsupported = !state->extensions->ARB_shader_texture_lod; } else if (strcmp(name, "GL_ARB_shader_stencil_export") == 0) { state->ARB_shader_stencil_export_enable = (ext_mode != extension_disable); state->ARB_shader_stencil_export_warn = (ext_mode == extension_warn); diff --git a/src/glsl/glsl_parser_extras.h b/src/glsl/glsl_parser_extras.h index f9147653f35..878d2ae3f4d 100644 --- a/src/glsl/glsl_parser_extras.h +++ b/src/glsl/glsl_parser_extras.h @@ -168,6 +168,8 @@ struct _mesa_glsl_parse_state { unsigned ARB_texture_rectangle_warn:1; unsigned EXT_texture_array_enable:1; unsigned EXT_texture_array_warn:1; + unsigned ARB_shader_texture_lod_enable:1; + unsigned ARB_shader_texture_lod_warn:1; unsigned ARB_shader_stencil_export_enable:1; unsigned ARB_shader_stencil_export_warn:1; unsigned AMD_conservative_depth_enable:1; diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index effcb6c1c4a..fd5227d2c55 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -663,11 +663,14 @@ #define BRW_MESSAGE_TARGET_MATH 1 /* reserved on GEN6 */ #define BRW_MESSAGE_TARGET_SAMPLER 2 #define BRW_MESSAGE_TARGET_GATEWAY 3 -#define BRW_MESSAGE_TARGET_DATAPORT_READ 4 /* sampler cache on GEN6 */ -#define BRW_MESSAGE_TARGET_DATAPORT_WRITE 5 /* render cache on Gen6 */ +#define BRW_MESSAGE_TARGET_DATAPORT_READ 4 +#define BRW_MESSAGE_TARGET_DATAPORT_WRITE 5 #define BRW_MESSAGE_TARGET_URB 6 #define BRW_MESSAGE_TARGET_THREAD_SPAWNER 7 -#define BRW_MESSAGE_TARGET_CONST_CACHE 9 /* GEN6 */ + +#define GEN6_MESSAGE_TARGET_DP_SAMPLER_CACHE 4 +#define GEN6_MESSAGE_TARGET_DP_RENDER_CACHE 5 +#define GEN6_MESSAGE_TARGET_DP_CONST_CACHE 9 #define BRW_SAMPLER_RETURN_FORMAT_FLOAT32 0 #define BRW_SAMPLER_RETURN_FORMAT_UINT32 2 @@ -749,7 +752,7 @@ #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 0 #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 1 -#define BRW_DATAPORT_WRITE_MESSAGE_DWORD_BLOCK_WRITE 2 +#define BRW_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 2 #define BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 3 #define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 4 #define BRW_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE 5 @@ -760,7 +763,7 @@ #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 8 #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 9 #define GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 10 -#define GEN6_DATAPORT_WRITE_MESSAGE_DWORLD_SCATTERED_WRITE 11 +#define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 11 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 12 #define GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE 13 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE 14 diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c index 111cb9974e1..af41c848308 100644 --- a/src/mesa/drivers/dri/i965/brw_disasm.c +++ b/src/mesa/drivers/dri/i965/brw_disasm.c @@ -967,12 +967,12 @@ int brw_disasm (FILE *file, struct brw_instruction *inst, int gen) case BRW_MESSAGE_TARGET_DATAPORT_READ: if (gen >= 6) { format (file, " (%d, %d, %d, %d, %d, %d)", - inst->bits3.dp_render_cache.binding_table_index, - inst->bits3.dp_render_cache.msg_control, - inst->bits3.dp_render_cache.msg_type, - inst->bits3.dp_render_cache.send_commit_msg, - inst->bits3.dp_render_cache.msg_length, - inst->bits3.dp_render_cache.response_length); + inst->bits3.gen6_dp.binding_table_index, + inst->bits3.gen6_dp.msg_control, + inst->bits3.gen6_dp.msg_type, + inst->bits3.gen6_dp.send_commit_msg, + inst->bits3.gen6_dp.msg_length, + inst->bits3.gen6_dp.response_length); } else if (gen >= 5 /* FINISHME: || is_g4x */) { format (file, " (%d, %d, %d)", inst->bits3.dp_read_gen5.binding_table_index, @@ -988,12 +988,12 @@ int brw_disasm (FILE *file, struct brw_instruction *inst, int gen) case BRW_MESSAGE_TARGET_DATAPORT_WRITE: if (gen >= 6) { format (file, " (%d, %d, %d, %d, %d, %d)", - inst->bits3.dp_render_cache.binding_table_index, - inst->bits3.dp_render_cache.msg_control, - inst->bits3.dp_render_cache.msg_type, - inst->bits3.dp_render_cache.send_commit_msg, - inst->bits3.dp_render_cache.msg_length, - inst->bits3.dp_render_cache.response_length); + inst->bits3.gen6_dp.binding_table_index, + inst->bits3.gen6_dp.msg_control, + inst->bits3.gen6_dp.msg_type, + inst->bits3.gen6_dp.send_commit_msg, + inst->bits3.gen6_dp.msg_length, + inst->bits3.gen6_dp.response_length); } else { format (file, " (%d, %d, %d, %d)", inst->bits3.dp_write.binding_table_index, diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 859068ec4eb..633cc03388a 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -487,18 +487,18 @@ static void brw_set_dp_write_message( struct brw_context *brw, brw_set_src1(insn, brw_imm_ud(0)); if (intel->gen >= 6) { - insn->bits3.dp_render_cache.binding_table_index = binding_table_index; - insn->bits3.dp_render_cache.msg_control = msg_control; - insn->bits3.dp_render_cache.pixel_scoreboard_clear = pixel_scoreboard_clear; - insn->bits3.dp_render_cache.msg_type = msg_type; - insn->bits3.dp_render_cache.send_commit_msg = send_commit_msg; - insn->bits3.dp_render_cache.header_present = header_present; - insn->bits3.dp_render_cache.response_length = response_length; - insn->bits3.dp_render_cache.msg_length = msg_length; - insn->bits3.dp_render_cache.end_of_thread = end_of_thread; + insn->bits3.gen6_dp.binding_table_index = binding_table_index; + insn->bits3.gen6_dp.msg_control = msg_control; + insn->bits3.gen6_dp.pixel_scoreboard_clear = pixel_scoreboard_clear; + insn->bits3.gen6_dp.msg_type = msg_type; + insn->bits3.gen6_dp.send_commit_msg = send_commit_msg; + insn->bits3.gen6_dp.header_present = header_present; + insn->bits3.gen6_dp.response_length = response_length; + insn->bits3.gen6_dp.msg_length = msg_length; + insn->bits3.gen6_dp.end_of_thread = end_of_thread; /* We always use the render cache for write messages */ - insn->header.destreg__conditionalmod = BRW_MESSAGE_TARGET_DATAPORT_WRITE; + insn->header.destreg__conditionalmod = GEN6_MESSAGE_TARGET_DP_RENDER_CACHE; } else if (intel->gen == 5) { insn->bits3.dp_write_gen5.binding_table_index = binding_table_index; insn->bits3.dp_write_gen5.msg_control = msg_control; @@ -541,19 +541,19 @@ brw_set_dp_read_message(struct brw_context *brw, uint32_t target_function; if (target_cache == BRW_DATAPORT_READ_TARGET_DATA_CACHE) - target_function = BRW_MESSAGE_TARGET_DATAPORT_READ; /* data cache */ + target_function = GEN6_MESSAGE_TARGET_DP_SAMPLER_CACHE; else - target_function = BRW_MESSAGE_TARGET_DATAPORT_WRITE; /* render cache */ - - insn->bits3.dp_render_cache.binding_table_index = binding_table_index; - insn->bits3.dp_render_cache.msg_control = msg_control; - insn->bits3.dp_render_cache.pixel_scoreboard_clear = 0; - insn->bits3.dp_render_cache.msg_type = msg_type; - insn->bits3.dp_render_cache.send_commit_msg = 0; - insn->bits3.dp_render_cache.header_present = 1; - insn->bits3.dp_render_cache.response_length = response_length; - insn->bits3.dp_render_cache.msg_length = msg_length; - insn->bits3.dp_render_cache.end_of_thread = 0; + target_function = GEN6_MESSAGE_TARGET_DP_RENDER_CACHE; + + insn->bits3.gen6_dp.binding_table_index = binding_table_index; + insn->bits3.gen6_dp.msg_control = msg_control; + insn->bits3.gen6_dp.pixel_scoreboard_clear = 0; + insn->bits3.gen6_dp.msg_type = msg_type; + insn->bits3.gen6_dp.send_commit_msg = 0; + insn->bits3.gen6_dp.header_present = 1; + insn->bits3.gen6_dp.response_length = response_length; + insn->bits3.gen6_dp.msg_length = msg_length; + insn->bits3.gen6_dp.end_of_thread = 0; insn->header.destreg__conditionalmod = target_function; } else if (intel->gen == 5) { insn->bits3.dp_read_gen5.binding_table_index = binding_table_index; @@ -1711,7 +1711,7 @@ void brw_oword_block_read(struct brw_compile *p, bind_table_index, BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW, BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ, - 0, /* source cache = data cache */ + BRW_DATAPORT_READ_TARGET_DATA_CACHE, 1, /* msg_length */ 1); /* response_length (1 reg, 2 owords!) */ @@ -1752,7 +1752,7 @@ void brw_dword_scattered_read(struct brw_compile *p, bind_table_index, BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS, BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ, - 0, /* source cache = data cache */ + BRW_DATAPORT_READ_TARGET_DATA_CACHE, 2, /* msg_length */ 1); /* response_length */ } @@ -1806,7 +1806,7 @@ void brw_dp_READ_4_vs(struct brw_compile *p, bind_table_index, 0, BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ, /* msg_type */ - 0, /* source cache = data cache */ + BRW_DATAPORT_READ_TARGET_DATA_CACHE, 1, /* msg_length */ 1); /* response_length (1 Oword) */ } diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h index 8d4797fb675..6132bb91abe 100644 --- a/src/mesa/drivers/dri/i965/brw_structs.h +++ b/src/mesa/drivers/dri/i965/brw_structs.h @@ -1704,7 +1704,7 @@ struct brw_instruction GLuint msg_length:4; GLuint pad1:2; GLuint end_of_thread:1; - } dp_render_cache; + } gen6_dp; struct { GLuint function_control:16; diff --git a/src/mesa/drivers/dri/r300/compiler/Makefile b/src/mesa/drivers/dri/r300/compiler/Makefile index 5c9f57b4eac..4bedfacd632 100644 --- a/src/mesa/drivers/dri/r300/compiler/Makefile +++ b/src/mesa/drivers/dri/r300/compiler/Makefile @@ -74,6 +74,9 @@ tags: clean: rm -f $(OBJECTS) lib$(LIBNAME).a depend depend.bak +test: default + @$(MAKE) -s -C tests/ + # Dummy target install: @echo -n "" diff --git a/src/mesa/drivers/dri/r300/compiler/memory_pool.c b/src/mesa/drivers/dri/r300/compiler/memory_pool.c index 76c7c60d8f5..ddcdddf9e3c 100644 --- a/src/mesa/drivers/dri/r300/compiler/memory_pool.c +++ b/src/mesa/drivers/dri/r300/compiler/memory_pool.c @@ -28,7 +28,7 @@ #define POOL_LARGE_ALLOC 4096 -#define POOL_ALIGN 4 +#define POOL_ALIGN 8 struct memory_block { diff --git a/src/mesa/drivers/dri/r300/compiler/r3xx_fragprog.c b/src/mesa/drivers/dri/r300/compiler/r3xx_fragprog.c index e2441e97d87..bb6c010e8e3 100644 --- a/src/mesa/drivers/dri/r300/compiler/r3xx_fragprog.c +++ b/src/mesa/drivers/dri/r300/compiler/r3xx_fragprog.c @@ -109,8 +109,12 @@ void r3xx_compile_fragment_program(struct r300_fragment_program_compiler* c) { 0, 0 } }; - struct radeon_program_transformation native_rewrite_r500[] = { + struct radeon_program_transformation rewrite_if[] = { { &r500_transform_IF, 0 }, + {0, 0} + }; + + struct radeon_program_transformation native_rewrite_r500[] = { { &radeonTransformALU, 0 }, { &radeonTransformDeriv, 0 }, { &radeonTransformTrigScale, 0 }, @@ -135,6 +139,7 @@ void r3xx_compile_fragment_program(struct r300_fragment_program_compiler* c) {"emulate branches", 1, !is_r500, rc_emulate_branches, NULL}, {"saturate output writes", 1, sat_out, rc_local_transform, saturate_output}, {"transform TEX", 1, 1, rc_local_transform, rewrite_tex}, + {"transform IF", 1, is_r500, rc_local_transform, rewrite_if}, {"native rewrite", 1, is_r500, rc_local_transform, native_rewrite_r500}, {"native rewrite", 1, !is_r500, rc_local_transform, native_rewrite_r300}, {"deadcode", 1, opt, rc_dataflow_deadcode, dataflow_outputs_mark_use}, diff --git a/src/mesa/drivers/dri/r300/compiler/r500_fragprog.c b/src/mesa/drivers/dri/r300/compiler/r500_fragprog.c index 5e0be6b8881..cf99f5e4538 100644 --- a/src/mesa/drivers/dri/r300/compiler/r500_fragprog.c +++ b/src/mesa/drivers/dri/r300/compiler/r500_fragprog.c @@ -30,6 +30,8 @@ #include <stdio.h> #include "radeon_compiler_util.h" +#include "radeon_list.h" +#include "radeon_variable.h" #include "../r300_reg.h" /** @@ -37,27 +39,143 @@ */ int r500_transform_IF( struct radeon_compiler * c, - struct rc_instruction * inst, - void* data) + struct rc_instruction * inst_if, + void *data) { - struct rc_instruction * inst_mov; + struct rc_variable * writer; + struct rc_list * writer_list, * list_ptr; + struct rc_list * var_list = rc_get_variables(c); + unsigned int generic_if = 0; + unsigned int alu_chan; - if (inst->U.I.Opcode != RC_OPCODE_IF) + if (inst_if->U.I.Opcode != RC_OPCODE_IF) { return 0; + } + + writer_list = rc_variable_list_get_writers( + var_list, inst_if->Type, &inst_if->U.I.SrcReg[0]); + if (!writer_list) { + generic_if = 1; + } else { + + /* Make sure it is safe for the writers to write to + * ALU Result */ + for (list_ptr = writer_list; list_ptr; + list_ptr = list_ptr->Next) { + struct rc_instruction * inst; + writer = list_ptr->Item; + /* We are going to modify the destination register + * of writer, so if it has a reader other than + * inst_if (aka ReaderCount > 1) we must fall back to + * our generic IF. + * If the writer has a lower IP than inst_if, this + * means that inst_if is above the writer in a loop. + * I'm not sure why this would ever happen, but + * if it does we want to make sure we fall back + * to our generic IF. */ + if (writer->ReaderCount > 1 || writer->Inst->IP < inst_if->IP) { + generic_if = 1; + break; + } + + /* The ALU Result is not preserved across IF + * instructions, so if there is another IF + * instruction between writer and inst_if, then + * we need to fall back to generic IF. */ + for (inst = writer->Inst; inst != inst_if; inst = inst->Next) { + const struct rc_opcode_info * info = + rc_get_opcode_info(inst->U.I.Opcode); + if (info->IsFlowControl) { + generic_if = 1; + break; + } + } + if (generic_if) { + break; + } + } + } + + if (GET_SWZ(inst_if->U.I.SrcReg[0].Swizzle, 0) == RC_SWIZZLE_X) { + alu_chan = RC_ALURESULT_X; + } else { + alu_chan = RC_ALURESULT_W; + } + if (generic_if) { + struct rc_instruction * inst_mov = + rc_insert_new_instruction(c, inst_if->Prev); + + inst_mov->U.I.Opcode = RC_OPCODE_MOV; + inst_mov->U.I.DstReg.WriteMask = 0; + inst_mov->U.I.DstReg.File = RC_FILE_NONE; + inst_mov->U.I.ALUResultCompare = RC_COMPARE_FUNC_NOTEQUAL; + inst_mov->U.I.WriteALUResult = alu_chan; + inst_mov->U.I.SrcReg[0] = inst_if->U.I.SrcReg[0]; + if (alu_chan == RC_ALURESULT_X) { + inst_mov->U.I.SrcReg[0].Swizzle = combine_swizzles4( + inst_mov->U.I.SrcReg[0].Swizzle, + RC_SWIZZLE_X, RC_SWIZZLE_UNUSED, + RC_SWIZZLE_UNUSED, RC_SWIZZLE_UNUSED); + } else { + inst_mov->U.I.SrcReg[0].Swizzle = combine_swizzles4( + inst_mov->U.I.SrcReg[0].Swizzle, + RC_SWIZZLE_UNUSED, RC_SWIZZLE_UNUSED, + RC_SWIZZLE_UNUSED, RC_SWIZZLE_Z); + } + } else { + rc_compare_func compare_func = RC_COMPARE_FUNC_NEVER; + unsigned int reverse_srcs = 0; + unsigned int preserve_opcode = 0; + for (list_ptr = writer_list; list_ptr; + list_ptr = list_ptr->Next) { + writer = list_ptr->Item; + switch(writer->Inst->U.I.Opcode) { + case RC_OPCODE_SEQ: + compare_func = RC_COMPARE_FUNC_EQUAL; + break; + case RC_OPCODE_SNE: + compare_func = RC_COMPARE_FUNC_NOTEQUAL; + break; + case RC_OPCODE_SLE: + reverse_srcs = 1; + /* Fall through */ + case RC_OPCODE_SGE: + compare_func = RC_COMPARE_FUNC_GEQUAL; + break; + case RC_OPCODE_SGT: + reverse_srcs = 1; + /* Fall through */ + case RC_OPCODE_SLT: + compare_func = RC_COMPARE_FUNC_LESS; + break; + default: + compare_func = RC_COMPARE_FUNC_NOTEQUAL; + preserve_opcode = 1; + break; + } + if (!preserve_opcode) { + writer->Inst->U.I.Opcode = RC_OPCODE_SUB; + } + writer->Inst->U.I.DstReg.WriteMask = 0; + writer->Inst->U.I.DstReg.File = RC_FILE_NONE; + writer->Inst->U.I.WriteALUResult = alu_chan; + writer->Inst->U.I.ALUResultCompare = compare_func; + if (reverse_srcs) { + struct rc_src_register temp_src; + temp_src = writer->Inst->U.I.SrcReg[0]; + writer->Inst->U.I.SrcReg[0] = + writer->Inst->U.I.SrcReg[1]; + writer->Inst->U.I.SrcReg[1] = temp_src; + } + } + } - inst_mov = rc_insert_new_instruction(c, inst->Prev); - inst_mov->U.I.Opcode = RC_OPCODE_MOV; - inst_mov->U.I.DstReg.WriteMask = 0; - inst_mov->U.I.WriteALUResult = RC_ALURESULT_W; - inst_mov->U.I.ALUResultCompare = RC_COMPARE_FUNC_NOTEQUAL; - inst_mov->U.I.SrcReg[0] = inst->U.I.SrcReg[0]; - inst_mov->U.I.SrcReg[0].Swizzle = combine_swizzles4(inst_mov->U.I.SrcReg[0].Swizzle, - RC_SWIZZLE_UNUSED, RC_SWIZZLE_UNUSED, RC_SWIZZLE_UNUSED, RC_SWIZZLE_X); - - inst->U.I.SrcReg[0].File = RC_FILE_SPECIAL; - inst->U.I.SrcReg[0].Index = RC_SPECIAL_ALU_RESULT; - inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZW; - inst->U.I.SrcReg[0].Negate = 0; + inst_if->U.I.SrcReg[0].File = RC_FILE_SPECIAL; + inst_if->U.I.SrcReg[0].Index = RC_SPECIAL_ALU_RESULT; + inst_if->U.I.SrcReg[0].Swizzle = RC_MAKE_SWIZZLE( + RC_SWIZZLE_X, RC_SWIZZLE_UNUSED, + RC_SWIZZLE_UNUSED, RC_SWIZZLE_UNUSED); + inst_if->U.I.SrcReg[0].Negate = 0; return 1; } diff --git a/src/mesa/drivers/dri/r300/compiler/r500_fragprog.h b/src/mesa/drivers/dri/r300/compiler/r500_fragprog.h index 1e665e27641..6aa448cc6f7 100644 --- a/src/mesa/drivers/dri/r300/compiler/r500_fragprog.h +++ b/src/mesa/drivers/dri/r300/compiler/r500_fragprog.h @@ -44,7 +44,7 @@ extern struct rc_swizzle_caps r500_swizzle_caps; extern int r500_transform_IF( struct radeon_compiler * c, - struct rc_instruction * inst, + struct rc_instruction * inst_if, void* data); #endif diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_compiler_util.c b/src/mesa/drivers/dri/r300/compiler/radeon_compiler_util.c index b077e7b7d65..c8001ba8c18 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_compiler_util.c +++ b/src/mesa/drivers/dri/r300/compiler/radeon_compiler_util.c @@ -359,53 +359,71 @@ unsigned int rc_source_type_mask(unsigned int mask) return ret; } +struct src_select { + rc_register_file File; + int Index; + unsigned int SrcType; +}; + struct can_use_presub_data { - struct rc_src_register RemoveSrcs[3]; - unsigned int RGBCount; - unsigned int AlphaCount; + struct src_select Selects[5]; + unsigned int SelectCount; + const struct rc_src_register * ReplaceReg; + unsigned int ReplaceRemoved; }; +static void can_use_presub_data_add_select( + struct can_use_presub_data * data, + rc_register_file file, + unsigned int index, + unsigned int src_type) +{ + struct src_select * select; + + select = &data->Selects[data->SelectCount++]; + select->File = file; + select->Index = index; + select->SrcType = src_type; +} + +/** + * This callback function counts the number of sources in inst that are + * different from the sources in can_use_presub_data->RemoveSrcs. + */ static void can_use_presub_read_cb( void * userdata, struct rc_instruction * inst, - rc_register_file file, - unsigned int index, - unsigned int mask) + struct rc_src_register * src) { struct can_use_presub_data * d = userdata; - unsigned int src_type = rc_source_type_mask(mask); - unsigned int i; - if (file == RC_FILE_NONE) + if (!d->ReplaceRemoved && src == d->ReplaceReg) { + d->ReplaceRemoved = 1; return; - - for(i = 0; i < 3; i++) { - if (d->RemoveSrcs[i].File == file - && d->RemoveSrcs[i].Index == index) { - src_type &= - ~rc_source_type_swz(d->RemoveSrcs[i].Swizzle); - } } - if (src_type & RC_SOURCE_RGB) - d->RGBCount++; + if (src->File == RC_FILE_NONE) + return; - if (src_type & RC_SOURCE_ALPHA) - d->AlphaCount++; + can_use_presub_data_add_select(d, src->File, src->Index, + rc_source_type_swz(src->Swizzle)); } unsigned int rc_inst_can_use_presub( struct rc_instruction * inst, rc_presubtract_op presub_op, unsigned int presub_writemask, - struct rc_src_register replace_reg, - struct rc_src_register presub_src0, - struct rc_src_register presub_src1) + const struct rc_src_register * replace_reg, + const struct rc_src_register * presub_src0, + const struct rc_src_register * presub_src1) { struct can_use_presub_data d; unsigned int num_presub_srcs; + unsigned int i; const struct rc_opcode_info * info = rc_get_opcode_info(inst->U.I.Opcode); + int rgb_count = 0, alpha_count = 0; + unsigned int src_type0, src_type1; if (presub_op == RC_PRESUB_NONE) { return 1; @@ -425,15 +443,62 @@ unsigned int rc_inst_can_use_presub( } memset(&d, 0, sizeof(d)); - d.RemoveSrcs[0] = replace_reg; - d.RemoveSrcs[1] = presub_src0; - d.RemoveSrcs[2] = presub_src1; + d.ReplaceReg = replace_reg; - rc_for_all_reads_mask(inst, can_use_presub_read_cb, &d); + rc_for_all_reads_src(inst, can_use_presub_read_cb, &d); num_presub_srcs = rc_presubtract_src_reg_count(presub_op); - if (d.RGBCount + num_presub_srcs > 3 || d.AlphaCount + num_presub_srcs > 3) { + src_type0 = rc_source_type_swz(presub_src0->Swizzle); + can_use_presub_data_add_select(&d, + presub_src0->File, + presub_src0->Index, + src_type0); + + if (num_presub_srcs > 1) { + src_type1 = rc_source_type_swz(presub_src1->Swizzle); + can_use_presub_data_add_select(&d, + presub_src1->File, + presub_src1->Index, + src_type1); + + /* Even if both of the presub sources read from the same + * register, we still need to use 2 different source selects + * for them, so we need to increment the count to compensate. + */ + if (presub_src0->File == presub_src1->File + && presub_src0->Index == presub_src1->Index) { + if (src_type0 & src_type1 & RC_SOURCE_RGB) { + rgb_count++; + } + if (src_type0 & src_type1 & RC_SOURCE_ALPHA) { + alpha_count++; + } + } + } + + /* Count the number of source selects for Alpha and RGB. If we + * encounter two of the same source selects then we can ignore the + * first one. */ + for (i = 0; i < d.SelectCount; i++) { + unsigned int j; + unsigned int src_type = d.Selects[i].SrcType; + for (j = i + 1; j < d.SelectCount; j++) { + if (d.Selects[i].File == d.Selects[j].File + && d.Selects[i].Index == d.Selects[j].Index) { + src_type &= ~d.Selects[j].SrcType; + } + } + if (src_type & RC_SOURCE_RGB) { + rgb_count++; + } + + if (src_type & RC_SOURCE_ALPHA) { + alpha_count++; + } + } + + if (rgb_count > 3 || alpha_count > 3) { return 0; } diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_compiler_util.h b/src/mesa/drivers/dri/r300/compiler/radeon_compiler_util.h index 2af289dfabd..3730aa888c0 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_compiler_util.h +++ b/src/mesa/drivers/dri/r300/compiler/radeon_compiler_util.h @@ -63,9 +63,9 @@ unsigned int rc_inst_can_use_presub( struct rc_instruction * inst, rc_presubtract_op presub_op, unsigned int presub_writemask, - struct rc_src_register replace_reg, - struct rc_src_register presub_src0, - struct rc_src_register presub_src1); + const struct rc_src_register * replace_reg, + const struct rc_src_register * presub_src0, + const struct rc_src_register * presub_src1); int rc_get_max_index( struct radeon_compiler * c, diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_optimize.c b/src/mesa/drivers/dri/r300/compiler/radeon_optimize.c index 5b4fba80873..ac73608839e 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_optimize.c +++ b/src/mesa/drivers/dri/r300/compiler/radeon_optimize.c @@ -70,9 +70,9 @@ static void copy_propagate_scan_read(void * data, struct rc_instruction * inst, if(!rc_inst_can_use_presub(inst, reader_data->Writer->U.I.PreSub.Opcode, rc_swizzle_to_writemask(src->Swizzle), - *src, - reader_data->Writer->U.I.PreSub.SrcReg[0], - reader_data->Writer->U.I.PreSub.SrcReg[1])) { + src, + &reader_data->Writer->U.I.PreSub.SrcReg[0], + &reader_data->Writer->U.I.PreSub.SrcReg[1])) { reader_data->Abort = 1; return; } @@ -437,9 +437,9 @@ static void presub_scan_read( if (!rc_inst_can_use_presub(inst, *presub_opcode, reader_data->Writer->U.I.DstReg.WriteMask, - *src, - reader_data->Writer->U.I.SrcReg[0], - reader_data->Writer->U.I.SrcReg[1])) { + src, + &reader_data->Writer->U.I.SrcReg[0], + &reader_data->Writer->U.I.SrcReg[1])) { reader_data->Abort = 1; return; } @@ -517,8 +517,11 @@ static int is_presub_candidate( assert(inst->U.I.Opcode == RC_OPCODE_ADD); - if (inst->U.I.PreSub.Opcode != RC_PRESUB_NONE || inst->U.I.SaturateMode) + if (inst->U.I.PreSub.Opcode != RC_PRESUB_NONE + || inst->U.I.SaturateMode + || inst->U.I.WriteALUResult) { return 0; + } /* If both sources use a constant swizzle, then we can't convert it to * a presubtract operation. In fact for the ADD and SUB presubtract diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_variable.c b/src/mesa/drivers/dri/r300/compiler/radeon_variable.c index 16fa5d28902..33181bdcc88 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_variable.c +++ b/src/mesa/drivers/dri/r300/compiler/radeon_variable.c @@ -388,17 +388,21 @@ struct rc_list * rc_get_variables(struct radeon_compiler * c) */ while (aborted_list) { struct rc_list * search_ptr_next; + struct rc_variable * var; var_ptr = aborted_list; + for (var = var_ptr->Item; var; var = var->Friend) { - search_ptr = var_ptr->Next; - while(search_ptr) { - search_ptr_next = search_ptr->Next; - if (readers_intersect(var_ptr->Item, search_ptr->Item)){ - rc_list_remove(&aborted_list, search_ptr); - rc_variable_add_friend(var_ptr->Item, + search_ptr = var_ptr->Next; + while(search_ptr) { + search_ptr_next = search_ptr->Next; + if (readers_intersect(var, search_ptr->Item)){ + rc_list_remove(&aborted_list, + search_ptr); + rc_variable_add_friend(var, search_ptr->Item); + } + search_ptr = search_ptr_next; } - search_ptr = search_ptr_next; } rc_list_remove(&aborted_list, var_ptr); rc_list_add(&variable_list, rc_list( @@ -465,6 +469,67 @@ struct rc_list * rc_variable_readers_union(struct rc_variable * var) return list; } +static unsigned int reader_equals_src( + struct rc_reader reader, + unsigned int src_type, + void * src) +{ + if (reader.Inst->Type != src_type) { + return 0; + } + if (src_type == RC_INSTRUCTION_NORMAL) { + return reader.U.I.Src == src; + } else { + return reader.U.P.Src == src; + } +} + +static unsigned int variable_writes_src( + struct rc_variable * var, + unsigned int src_type, + void * src) +{ + unsigned int i; + for (i = 0; i < var->ReaderCount; i++) { + if (reader_equals_src(var->Readers[i], src_type, src)) { + return 1; + } + } + return 0; +} + + +struct rc_list * rc_variable_list_get_writers( + struct rc_list * var_list, + unsigned int src_type, + void * src) +{ + struct rc_list * list_ptr; + struct rc_list * writer_list = NULL; + for (list_ptr = var_list; list_ptr; list_ptr = list_ptr->Next) { + struct rc_variable * var = list_ptr->Item; + if (variable_writes_src(var, src_type, src)) { + struct rc_variable * friend; + rc_list_add(&writer_list, rc_list(&var->C->Pool, var)); + for (friend = var->Friend; friend; + friend = friend->Friend) { + if (variable_writes_src(friend, src_type, src)) { + rc_list_add(&writer_list, + rc_list(&var->C->Pool, friend)); + } + } + /* Once we have indentifed the variable and its + * friends that write this source, we can stop + * stop searching, because we know know of the + * other variables in the list will write this source. + * If they did they would be friends of var. + */ + break; + } + } + return writer_list; +} + void rc_variable_print(struct rc_variable * var) { unsigned int i; diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_variable.h b/src/mesa/drivers/dri/r300/compiler/radeon_variable.h index b8fbcaa4029..9427bee18a7 100644 --- a/src/mesa/drivers/dri/r300/compiler/radeon_variable.h +++ b/src/mesa/drivers/dri/r300/compiler/radeon_variable.h @@ -79,6 +79,11 @@ unsigned int rc_variable_writemask_sum(struct rc_variable * var); struct rc_list * rc_variable_readers_union(struct rc_variable * var); +struct rc_list * rc_variable_list_get_writers( + struct rc_list * var_list, + unsigned int src_type, + void * src); + void rc_variable_print(struct rc_variable * var); #endif /* RADEON_VARIABLE_H */ diff --git a/src/mesa/drivers/dri/r300/compiler/tests/Makefile b/src/mesa/drivers/dri/r300/compiler/tests/Makefile new file mode 100644 index 00000000000..e268543e6e7 --- /dev/null +++ b/src/mesa/drivers/dri/r300/compiler/tests/Makefile @@ -0,0 +1,55 @@ +# src/mesa/drivers/dri/r300/compiler/Makefile + +TOP = ../../../../../../.. +include $(TOP)/configs/current + +CFLAGS += -Wall -Werror + +### Basic defines ### +TESTS = radeon_compiler_util_tests + +TEST_SOURCES := $(TESTS:=.c) + +SHARED_SOURCES = \ + rc_test_helpers.c \ + unit_test.c + +C_SOURCES = $(SHARED_SOURCES) $(TEST_SOURCES) + +INCLUDES = \ + -I. \ + -I.. + +COMPILER_LIB = ../libr300compiler.a + +##### TARGETS ##### + +default: depend run_tests + +depend: $(C_SOURCES) + rm -f depend + touch depend + $(MKDEP) $(MKDEP_OPTIONS) $(INCLUDES) $^ 2> /dev/null + +# Remove .o and backup files +clean: + rm -f $(TESTS) depend depend.bak + +$(TESTS): $(TESTS:=.o) $(SHARED_SOURCES:.c=.o) $(COMPILER_LIB) + $(APP_CC) -o $@ $^ + +run_tests: $(TESTS) + @echo "RUNNING TESTS:" + @echo "" + $(foreach test, $^, @./$(test)) + +.PHONY: $(COMPILER_LIB) +$(COMPILER_LIB): + $(MAKE) -C .. + +##### RULES ##### +.c.o: + $(CC) -c $(INCLUDES) $(CFLAGS) $(LIBRARY_DEFINES) $< -o $@ + + +sinclude depend diff --git a/src/mesa/drivers/dri/r300/compiler/tests/radeon_compiler_util_tests.c b/src/mesa/drivers/dri/r300/compiler/tests/radeon_compiler_util_tests.c new file mode 100644 index 00000000000..a2e3f2ab2e5 --- /dev/null +++ b/src/mesa/drivers/dri/r300/compiler/tests/radeon_compiler_util_tests.c @@ -0,0 +1,76 @@ +#include <stdlib.h> +#include <string.h> +#include <sys/types.h> + +#include "radeon_compiler_util.h" +#include "radeon_program.h" + +#include "rc_test_helpers.h" +#include "unit_test.h" + +static void test_rc_inst_can_use_presub( + struct test_result * result, + int expected, + const char * add_str, + const char * replace_str) +{ + struct rc_instruction add_inst, replace_inst; + int ret; + + test_begin(result); + init_rc_normal_instruction(&add_inst, add_str); + init_rc_normal_instruction(&replace_inst, replace_str); + + ret = rc_inst_can_use_presub(&replace_inst, RC_PRESUB_ADD, 0, + &replace_inst.U.I.SrcReg[0], + &add_inst.U.I.SrcReg[0], &add_inst.U.I.SrcReg[1]); + + test_check(result, ret == expected); +} + +static void test_runner_rc_inst_can_use_presub(struct test_result * result) +{ + + /* This tests the case where the source being replace has the same + * register file and register index as another source register in the + * CMP instruction. A previous version of this function was ignoring + * all registers that shared the same file and index as the replacement + * register when counting the number of source selects. + * + * https://bugs.freedesktop.org/show_bug.cgi?id=36527 + */ + test_rc_inst_can_use_presub(result, 0, + "ADD temp[0].z, temp[6].__x_, const[1].__x_;", + "CMP temp[0].y, temp[0]._z__, const[0]._z__, temp[0]._y__;"); + + + /* Testing a random case that should fail + * + * https://bugs.freedesktop.org/show_bug.cgi?id=36527 + */ + test_rc_inst_can_use_presub(result, 0, + "ADD temp[3], temp[1], temp[2];", + "MAD temp[1], temp[0], const[0].xxxx, -temp[3];"); + + /* This tests the case where the arguments of the ADD + * instruction share the same register file and index. Normally, we + * would need only one source select for these two arguments, but since + * they will be part of a presubtract operation we need to use the two + * source selects that the presubtract instruction expects + * (src0 and src1). + * + * https://bugs.freedesktop.org/show_bug.cgi?id=36527 + */ + test_rc_inst_can_use_presub(result, 0, + "ADD temp[3].x, temp[0].x___, temp[0].x___;", + "MAD temp[0].xyz, temp[2].xyz_, -temp[3].xxx_, input[5].xyz_;"); +} + +int main(int argc, char ** argv) +{ + struct test tests[] = { + {"rc_inst_can_use_presub()", test_runner_rc_inst_can_use_presub}, + {NULL, NULL} + }; + run_tests(tests); +} diff --git a/src/mesa/drivers/dri/r300/compiler/tests/rc_test_helpers.c b/src/mesa/drivers/dri/r300/compiler/tests/rc_test_helpers.c new file mode 100644 index 00000000000..ca4738af54d --- /dev/null +++ b/src/mesa/drivers/dri/r300/compiler/tests/rc_test_helpers.c @@ -0,0 +1,380 @@ +#include <errno.h> +#include <regex.h> +#include <stdlib.h> +#include <stdio.h> +#include <string.h> +#include <sys/types.h> + +#include "../radeon_compiler_util.h" +#include "../radeon_opcodes.h" +#include "../radeon_program.h" + +#include "rc_test_helpers.h" + +/* This file contains some helper functions for filling out the rc_instruction + * data structures. These functions take a string as input based on the format + * output by rc_program_print(). + */ + +#define VERBOSE 0 + +#define DBG(...) do { if (VERBOSE) fprintf(stderr, __VA_ARGS__); } while(0) + +#define REGEX_ERR_BUF_SIZE 50 + +struct match_info { + const char * String; + int Length; +}; + +static int match_length(regmatch_t * matches, int index) +{ + return matches[index].rm_eo - matches[index].rm_so; +} + +static int regex_helper( + const char * regex_str, + const char * search_str, + regmatch_t * matches, + int num_matches) +{ + char err_buf[REGEX_ERR_BUF_SIZE]; + regex_t regex; + int err_code; + unsigned int i; + + err_code = regcomp(®ex, regex_str, REG_EXTENDED); + if (err_code) { + regerror(err_code, ®ex, err_buf, REGEX_ERR_BUF_SIZE); + fprintf(stderr, "Failed to compile regex: %s\n", err_buf); + return 0; + } + + err_code = regexec(®ex, search_str, num_matches, matches, 0); + DBG("Search string: '%s'\n", search_str); + for (i = 0; i < num_matches; i++) { + DBG("Match %u start = %d end = %d\n", i, + matches[i].rm_so, matches[i].rm_eo); + } + if (err_code) { + regerror(err_code, ®ex, err_buf, REGEX_ERR_BUF_SIZE); + fprintf(stderr, "Failed to match regex: %s\n", err_buf); + return 0; + } + return 1; +} + +#define REGEX_SRC_MATCHES 6 + +struct src_tokens { + struct match_info Negate; + struct match_info Abs; + struct match_info File; + struct match_info Index; + struct match_info Swizzle; +}; + +/** + * Initialize the source register at index src_index for the instruction based + * on src_str. + * + * NOTE: Warning in init_rc_normal_instruction() applies to this function as + * well. + * + * @param src_str A string that represents the source register. The format for + * this string is the same that is output by rc_program_print. + * @return 1 On success, 0 on failure + */ +int init_rc_normal_src( + struct rc_instruction * inst, + unsigned int src_index, + const char * src_str) +{ + const char * regex_str = "(-*)(\\|*)([[:lower:]]*)\\[([[:digit:]])\\](\\.*[[:lower:]-]*)"; + regmatch_t matches[REGEX_SRC_MATCHES]; + struct src_tokens tokens; + struct rc_src_register * src_reg = &inst->U.I.SrcReg[src_index]; + unsigned int i; + + /* Execute the regex */ + if (!regex_helper(regex_str, src_str, matches, REGEX_SRC_MATCHES)) { + fprintf(stderr, "Failed to execute regex for src register.\n"); + return 0; + } + + /* Create Tokens */ + tokens.Negate.String = src_str + matches[1].rm_so; + tokens.Negate.Length = match_length(matches, 1); + tokens.Abs.String = src_str + matches[2].rm_so; + tokens.Abs.Length = match_length(matches, 2); + tokens.File.String = src_str + matches[3].rm_so; + tokens.File.Length = match_length(matches, 3); + tokens.Index.String = src_str + matches[4].rm_so; + tokens.Index.Length = match_length(matches, 4); + tokens.Swizzle.String = src_str + matches[5].rm_so; + tokens.Swizzle.Length = match_length(matches, 5); + + /* Negate */ + if (tokens.Negate.Length > 0) { + src_reg->Negate = RC_MASK_XYZW; + } + + /* Abs */ + if (tokens.Abs.Length > 0) { + src_reg->Abs = 1; + } + + /* File */ + if (!strncmp(tokens.File.String, "temp", tokens.File.Length)) { + src_reg->File = RC_FILE_TEMPORARY; + } else if (!strncmp(tokens.File.String, "input", tokens.File.Length)) { + src_reg->File = RC_FILE_INPUT; + } else if (!strncmp(tokens.File.String, "const", tokens.File.Length)) { + src_reg->File = RC_FILE_CONSTANT; + } else if (!strncmp(tokens.File.String, "none", tokens.File.Length)) { + src_reg->File = RC_FILE_NONE; + } + + /* Index */ + errno = 0; + src_reg->Index = strtol(tokens.Index.String, NULL, 10); + if (errno > 0) { + fprintf(stderr, "Could not convert src register index.\n"); + return 0; + } + + /* Swizzle */ + if (tokens.Swizzle.Length == 0) { + src_reg->Swizzle = RC_SWIZZLE_XYZW; + } else { + int str_index = 1; + src_reg->Swizzle = RC_MAKE_SWIZZLE_SMEAR(RC_SWIZZLE_UNUSED); + if (tokens.Swizzle.String[0] != '.') { + fprintf(stderr, "First char of swizzle is not valid.\n"); + return 0; + } + for (i = 0; i < 4; i++, str_index++) { + if (tokens.Swizzle.String[str_index] == '-') { + src_reg->Negate |= (1 << i); + str_index++; + } + switch(tokens.Swizzle.String[str_index]) { + case 'x': + SET_SWZ(src_reg->Swizzle, i, RC_SWIZZLE_X); + break; + case 'y': + SET_SWZ(src_reg->Swizzle, i, RC_SWIZZLE_Y); + break; + case 'z': + SET_SWZ(src_reg->Swizzle, i, RC_SWIZZLE_Z); + break; + case 'w': + SET_SWZ(src_reg->Swizzle, i, RC_SWIZZLE_W); + break; + case '1': + SET_SWZ(src_reg->Swizzle, i, RC_SWIZZLE_ONE); + break; + case '0': + SET_SWZ(src_reg->Swizzle, i, RC_SWIZZLE_ZERO); + break; + case 'H': + SET_SWZ(src_reg->Swizzle, i, RC_SWIZZLE_HALF); + break; + case '_': + SET_SWZ(src_reg->Swizzle, i, RC_SWIZZLE_UNUSED); + break; + default: + fprintf(stderr, "Unknown src register swizzle.\n"); + return 0; + } + } + } + DBG("File=%u index=%u swizzle=%x negate=%u abs=%u\n", + src_reg->File, src_reg->Index, src_reg->Swizzle, + src_reg->Negate, src_reg->Abs); + return 1; +} + +#define REGEX_DST_MATCHES 4 + +struct dst_tokens { + struct match_info File; + struct match_info Index; + struct match_info WriteMask; +}; + +/** + * Initialize the destination for the instruction based on dst_str. + * + * NOTE: Warning in init_rc_normal_instruction() applies to this function as + * well. + * + * @param dst_str A string that represents the destination register. The format + * for this string is the same that is output by rc_program_print. + * @return 1 On success, 0 on failure + */ +int init_rc_normal_dst( + struct rc_instruction * inst, + const char * dst_str) +{ + const char * regex_str = "([[:lower:]]*)\\[([[:digit:]]*)\\](\\.*[[:lower:]]*)"; + regmatch_t matches[REGEX_DST_MATCHES]; + struct dst_tokens tokens; + unsigned int i; + + /* Execute the regex */ + if (!regex_helper(regex_str, dst_str, matches, REGEX_DST_MATCHES)) { + fprintf(stderr, "Failed to execute regex for dst register.\n"); + return 0; + } + + /* Create Tokens */ + tokens.File.String = dst_str + matches[1].rm_so; + tokens.File.Length = match_length(matches, 1); + tokens.Index.String = dst_str + matches[2].rm_so; + tokens.Index.Length = match_length(matches, 2); + tokens.WriteMask.String = dst_str + matches[3].rm_so; + tokens.WriteMask.Length = match_length(matches, 3); + + /* File Type */ + if (!strncmp(tokens.File.String, "temp", tokens.File.Length)) { + inst->U.I.DstReg.File = RC_FILE_TEMPORARY; + } else if (!strncmp(tokens.File.String, "output", tokens.File.Length)) { + inst->U.I.DstReg.File = RC_FILE_OUTPUT; + } else { + fprintf(stderr, "Unknown dst register file type.\n"); + return 0; + } + + /* File Index */ + errno = 0; + inst->U.I.DstReg.Index = strtol(tokens.Index.String, NULL, 10); + + if (errno > 0) { + fprintf(stderr, "Could not convert dst register index\n"); + return 0; + } + + /* WriteMask */ + if (tokens.WriteMask.Length == 0) { + inst->U.I.DstReg.WriteMask = RC_MASK_XYZW; + } else { + /* The first character should be '.' */ + if (tokens.WriteMask.String[0] != '.') { + fprintf(stderr, "1st char of writemask is not valid.\n"); + return 0; + } + for (i = 1; i < tokens.WriteMask.Length; i++) { + switch(tokens.WriteMask.String[i]) { + case 'x': + inst->U.I.DstReg.WriteMask |= RC_MASK_X; + break; + case 'y': + inst->U.I.DstReg.WriteMask |= RC_MASK_Y; + break; + case 'z': + inst->U.I.DstReg.WriteMask |= RC_MASK_Z; + break; + case 'w': + inst->U.I.DstReg.WriteMask |= RC_MASK_W; + break; + default: + fprintf(stderr, "Unknown swizzle in writemask.\n"); + return 0; + } + } + } + DBG("Dst Reg File=%u Index=%d Writemask=%d\n", + inst->U.I.DstReg.File, + inst->U.I.DstReg.Index, + inst->U.I.DstReg.WriteMask); + return 1; +} + +#define REGEX_INST_MATCHES 7 + +struct inst_tokens { + struct match_info Opcode; + struct match_info Sat; + struct match_info Dst; + struct match_info Srcs[3]; +}; + +/** + * Initialize a normal instruction based on inst_str. + * + * WARNING: This function might not be able to handle every kind of format that + * rc_program_print() can output. If you are having problems with a + * particular string, you may need to add support for it to this functions. + * + * @param inst_str A string that represents the source register. The format for + * this string is the same that is output by rc_program_print. + * @return 1 On success, 0 on failure + */ +int init_rc_normal_instruction( + struct rc_instruction * inst, + const char * inst_str) +{ + const char * regex_str = "([[:upper:]]+)(_SAT)* ([^,]*)[, ]*([^,]*)[, ]*([^,]*)[, ]*([^;]*)"; + int i; + regmatch_t matches[REGEX_INST_MATCHES]; + struct inst_tokens tokens; + + /* Initialize inst */ + memset(inst, 0, sizeof(struct rc_instruction)); + inst->Type = RC_INSTRUCTION_NORMAL; + + /* Execute the regex */ + if (!regex_helper(regex_str, inst_str, matches, REGEX_INST_MATCHES)) { + return 0; + } + memset(&tokens, 0, sizeof(tokens)); + + /* Create Tokens */ + tokens.Opcode.String = inst_str + matches[1].rm_so; + tokens.Opcode.Length = match_length(matches, 1); + if (matches[2].rm_so > -1) { + tokens.Sat.String = inst_str + matches[2].rm_so; + tokens.Sat.Length = match_length(matches, 2); + } + + + /* Fill out the rest of the instruction. */ + for (i = 0; i < MAX_RC_OPCODE; i++) { + const struct rc_opcode_info * info = rc_get_opcode_info(i); + unsigned int first_src = 3; + unsigned int j; + if (strncmp(tokens.Opcode.String, info->Name, tokens.Opcode.Length)) { + continue; + } + inst->U.I.Opcode = info->Opcode; + if (info->HasDstReg) { + char * dst_str; + tokens.Dst.String = inst_str + matches[3].rm_so; + tokens.Dst.Length = match_length(matches, 3); + first_src++; + + dst_str = malloc(sizeof(char) * (tokens.Dst.Length + 1)); + strncpy(dst_str, tokens.Dst.String, tokens.Dst.Length); + dst_str[tokens.Dst.Length] = '\0'; + init_rc_normal_dst(inst, dst_str); + free(dst_str); + } + for (j = 0; j < info->NumSrcRegs; j++) { + char * src_str; + tokens.Srcs[j].String = + inst_str + matches[first_src + j].rm_so; + tokens.Srcs[j].Length = + match_length(matches, first_src + j); + + src_str = malloc(sizeof(char) * + (tokens.Srcs[j].Length + 1)); + strncpy(src_str, tokens.Srcs[j].String, + tokens.Srcs[j].Length); + src_str[tokens.Srcs[j].Length] = '\0'; + init_rc_normal_src(inst, j, src_str); + } + break; + } + return 1; +} diff --git a/src/mesa/drivers/dri/r300/compiler/tests/rc_test_helpers.h b/src/mesa/drivers/dri/r300/compiler/tests/rc_test_helpers.h new file mode 100644 index 00000000000..1a6bf9699ba --- /dev/null +++ b/src/mesa/drivers/dri/r300/compiler/tests/rc_test_helpers.h @@ -0,0 +1,13 @@ + +int init_rc_normal_src( + struct rc_instruction * inst, + unsigned int src_index, + const char * src_str); + +int init_rc_normal_dst( + struct rc_instruction * inst, + const char * dst_str); + +int init_rc_normal_instruction( + struct rc_instruction * inst, + const char * inst_str); diff --git a/src/mesa/drivers/dri/r300/compiler/tests/unit_test.c b/src/mesa/drivers/dri/r300/compiler/tests/unit_test.c new file mode 100644 index 00000000000..266f3365c58 --- /dev/null +++ b/src/mesa/drivers/dri/r300/compiler/tests/unit_test.c @@ -0,0 +1,35 @@ +#include <stdlib.h> +#include <stdio.h> +#include <string.h> + +#include "unit_test.h" + +void run_tests(struct test tests[]) +{ + int i; + for (i = 0; tests[i].name; i++) { + printf("Test %s\n", tests[i].name); + memset(&tests[i].result, 0, sizeof(tests[i].result)); + tests[i].test_func(&tests[i].result); + printf("Test %s (%d/%d) pass\n", tests[i].name, + tests[i].result.pass, tests[i].result.test_count); + } +} + +void test_begin(struct test_result * result) +{ + result->test_count++; +} + +void test_check(struct test_result * result, int cond) +{ + printf("Subtest %u -> ", result->test_count); + if (cond) { + result->pass++; + printf("Pass"); + } else { + result->fail++; + printf("Fail"); + } + printf("\n"); +} diff --git a/src/mesa/drivers/dri/r300/compiler/tests/unit_test.h b/src/mesa/drivers/dri/r300/compiler/tests/unit_test.h new file mode 100644 index 00000000000..441e8b655a5 --- /dev/null +++ b/src/mesa/drivers/dri/r300/compiler/tests/unit_test.h @@ -0,0 +1,17 @@ + +struct test_result { + unsigned int test_count; + unsigned int pass; + unsigned int fail; +}; + +struct test { + const char * name; + void (*test_func)(struct test_result * result); + struct test_result result; +}; + +void run_tests(struct test tests[]); + +void test_begin(struct test_result * result); +void test_check(struct test_result * result, int cond); diff --git a/src/mesa/drivers/dri/r300/r300_blit.c b/src/mesa/drivers/dri/r300/r300_blit.c index 14e60866d93..c525f0ffe2f 100644 --- a/src/mesa/drivers/dri/r300/r300_blit.c +++ b/src/mesa/drivers/dri/r300/r300_blit.c @@ -118,6 +118,7 @@ static void create_fragment_program(struct r300_context *r300) inst->U.I.SrcReg[0].Negate = 0; inst->U.I.SrcReg[0].RelAddr = 0; inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZW; + inst->U.I.TexSwizzle = RC_SWIZZLE_XYZW; compiler.Base.Program.InputsRead = (1 << FRAG_ATTRIB_TEX0); compiler.OutputColor[0] = FRAG_RESULT_COLOR; diff --git a/src/mesa/drivers/dri/r300/radeon_mesa_to_rc.c b/src/mesa/drivers/dri/r300/radeon_mesa_to_rc.c index 232603ece59..b1dfccd22d0 100644 --- a/src/mesa/drivers/dri/r300/radeon_mesa_to_rc.c +++ b/src/mesa/drivers/dri/r300/radeon_mesa_to_rc.c @@ -170,6 +170,7 @@ static void translate_instruction(struct radeon_compiler * c, dest->U.I.TexSrcUnit = src->TexSrcUnit; dest->U.I.TexSrcTarget = translate_tex_target(src->TexSrcTarget); dest->U.I.TexShadow = src->TexShadow; + dest->U.I.TexSwizzle = RC_SWIZZLE_XYZW; } } diff --git a/src/mesa/main/compiler.h b/src/mesa/main/compiler.h index e17fd0ff6fd..743841be4ef 100644 --- a/src/mesa/main/compiler.h +++ b/src/mesa/main/compiler.h @@ -355,7 +355,7 @@ static INLINE GLuint CPU_TO_LE32(GLuint x) #ifndef M_PI -#define M_PI (3.1415926536) +#define M_PI (3.14159265358979323846) #endif #ifndef M_E @@ -366,10 +366,6 @@ static INLINE GLuint CPU_TO_LE32(GLuint x) #define M_LOG2E (1.4426950408889634074) #endif -#ifndef ONE_DIV_LN2 -#define ONE_DIV_LN2 (1.442695040888963456) -#endif - #ifndef ONE_DIV_SQRT_LN2 #define ONE_DIV_SQRT_LN2 (1.201122408786449815) #endif diff --git a/src/mesa/main/dlist.c b/src/mesa/main/dlist.c index 63653df4502..930236c0161 100644 --- a/src/mesa/main/dlist.c +++ b/src/mesa/main/dlist.c @@ -9784,9 +9784,9 @@ _mesa_create_save_table(void) SET_DeleteProgramsNV(table, _mesa_DeletePrograms); SET_GenProgramsNV(table, _mesa_GenPrograms); SET_IsProgramNV(table, _mesa_IsProgramARB); - SET_GetVertexAttribdvNV(table, _mesa_GetVertexAttribdvNV); - SET_GetVertexAttribfvNV(table, _mesa_GetVertexAttribfvNV); - SET_GetVertexAttribivNV(table, _mesa_GetVertexAttribivNV); + SET_GetVertexAttribdvARB(table, _mesa_GetVertexAttribdvARB); + SET_GetVertexAttribfvARB(table, _mesa_GetVertexAttribfvARB); + SET_GetVertexAttribivARB(table, _mesa_GetVertexAttribivARB); SET_GetVertexAttribPointervNV(table, _mesa_GetVertexAttribPointervNV); SET_ProgramEnvParameter4dARB(table, save_ProgramEnvParameter4dARB); SET_ProgramEnvParameter4dvARB(table, save_ProgramEnvParameter4dvARB); diff --git a/src/mesa/main/extensions.c b/src/mesa/main/extensions.c index a9ef8fa4cb7..8672ac2a730 100644 --- a/src/mesa/main/extensions.c +++ b/src/mesa/main/extensions.c @@ -112,6 +112,7 @@ static const struct extension extension_table[] = { { "GL_ARB_seamless_cube_map", o(ARB_seamless_cube_map), GL, 2009 }, { "GL_ARB_shader_objects", o(ARB_shader_objects), GL, 2002 }, { "GL_ARB_shader_stencil_export", o(ARB_shader_stencil_export), GL, 2009 }, + { "GL_ARB_shader_texture_lod", o(ARB_shader_texture_lod), GL, 2009 }, { "GL_ARB_shading_language_100", o(ARB_shading_language_100), GL, 2003 }, { "GL_ARB_shadow_ambient", o(ARB_shadow_ambient), GL, 2001 }, { "GL_ARB_shadow", o(ARB_shadow), GL, 2001 }, @@ -143,7 +144,6 @@ static const struct extension extension_table[] = { { "GL_ARB_vertex_shader", o(ARB_vertex_shader), GL, 2002 }, { "GL_ARB_vertex_type_2_10_10_10_rev", o(ARB_vertex_type_2_10_10_10_rev), GL, 2009 }, { "GL_ARB_window_pos", o(ARB_window_pos), GL, 2001 }, - /* EXT extensions */ { "GL_EXT_abgr", o(EXT_abgr), GL, 1995 }, { "GL_EXT_bgra", o(EXT_bgra), GL, 1995 }, diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h index 29c8cfd2363..eb2efc89aed 100644 --- a/src/mesa/main/mtypes.h +++ b/src/mesa/main/mtypes.h @@ -2793,6 +2793,7 @@ struct gl_extensions GLboolean ARB_seamless_cube_map; GLboolean ARB_shader_objects; GLboolean ARB_shader_stencil_export; + GLboolean ARB_shader_texture_lod; GLboolean ARB_shading_language_100; GLboolean ARB_shadow; GLboolean ARB_shadow_ambient; diff --git a/src/mesa/main/samplerobj.c b/src/mesa/main/samplerobj.c index 229267f8c94..f7774fdd7cb 100644 --- a/src/mesa/main/samplerobj.c +++ b/src/mesa/main/samplerobj.c @@ -132,7 +132,7 @@ _mesa_init_sampler_object(struct gl_sampler_object *sampObj, GLuint name) sampObj->CompareMode = GL_NONE; sampObj->CompareFunc = GL_LEQUAL; sampObj->CompareFailValue = 0.0; - sampObj->sRGBDecode = GL_FALSE; + sampObj->sRGBDecode = GL_DECODE_EXT; sampObj->CubeMapSeamless = GL_FALSE; sampObj->DepthMode = 0; } diff --git a/src/mesa/main/texobj.c b/src/mesa/main/texobj.c index f2d214f931b..fdf12817c9a 100644 --- a/src/mesa/main/texobj.c +++ b/src/mesa/main/texobj.c @@ -254,6 +254,7 @@ _mesa_copy_texture_object( struct gl_texture_object *dest, dest->Sampler.CompareFailValue = src->Sampler.CompareFailValue; dest->Sampler.CubeMapSeamless = src->Sampler.CubeMapSeamless; dest->Sampler.DepthMode = src->Sampler.DepthMode; + dest->Sampler.sRGBDecode = src->Sampler.sRGBDecode; dest->_MaxLevel = src->_MaxLevel; dest->_MaxLambda = src->_MaxLambda; dest->GenerateMipmap = src->GenerateMipmap; diff --git a/src/mesa/program/ir_to_mesa.cpp b/src/mesa/program/ir_to_mesa.cpp index bc10b455b8b..510aeab82da 100644 --- a/src/mesa/program/ir_to_mesa.cpp +++ b/src/mesa/program/ir_to_mesa.cpp @@ -1966,7 +1966,7 @@ ir_to_mesa_visitor::visit(ir_call *ir) void ir_to_mesa_visitor::visit(ir_texture *ir) { - src_reg result_src, coord, lod_info, projector; + src_reg result_src, coord, lod_info, projector, dx, dy; dst_reg result_dst, coord_dst; ir_to_mesa_instruction *inst = NULL; prog_opcode opcode = OPCODE_NOP; @@ -2008,6 +2008,12 @@ ir_to_mesa_visitor::visit(ir_texture *ir) lod_info = this->result; break; case ir_txd: + opcode = OPCODE_TXD; + ir->lod_info.grad.dPdx->accept(this); + dx = this->result; + ir->lod_info.grad.dPdy->accept(this); + dy = this->result; + break; case ir_txf: assert(!"GLSL 1.30 features unsupported"); break; @@ -2080,7 +2086,10 @@ ir_to_mesa_visitor::visit(ir_texture *ir) coord_dst.writemask = WRITEMASK_XYZW; } - inst = emit(ir, opcode, result_dst, coord); + if (opcode == OPCODE_TXD) + inst = emit(ir, opcode, result_dst, coord, dx, dy); + else + inst = emit(ir, opcode, result_dst, coord); if (ir->shadow_comparitor) inst->tex_shadow = GL_TRUE; diff --git a/src/mesa/program/prog_instruction.h b/src/mesa/program/prog_instruction.h index 669d7102980..db2b594e753 100644 --- a/src/mesa/program/prog_instruction.h +++ b/src/mesa/program/prog_instruction.h @@ -154,9 +154,9 @@ typedef enum prog_opcode { OPCODE_ARR, /* 2 */ OPCODE_BGNLOOP, /* opt */ OPCODE_BGNSUB, /* opt */ - OPCODE_BRA, /* 2 X */ + OPCODE_BRA, /* 2 */ OPCODE_BRK, /* 2 opt */ - OPCODE_CAL, /* 2 2 X */ + OPCODE_CAL, /* 2 2 opt */ OPCODE_CMP, /* X X */ OPCODE_CONT, /* opt */ OPCODE_COS, /* X 2 X X */ @@ -168,7 +168,7 @@ typedef enum prog_opcode { OPCODE_DP4, /* X X X X X */ OPCODE_DPH, /* X X 1.1 */ OPCODE_DST, /* X X X X */ - OPCODE_ELSE, /* X */ + OPCODE_ELSE, /* opt */ OPCODE_EMIT_VERTEX,/* X */ OPCODE_END, /* X X X X opt */ OPCODE_END_PRIMITIVE,/* X */ @@ -176,16 +176,16 @@ typedef enum prog_opcode { OPCODE_ENDLOOP, /* opt */ OPCODE_ENDSUB, /* opt */ OPCODE_EX2, /* X X 2 X X */ - OPCODE_EXP, /* X X X */ + OPCODE_EXP, /* X X */ OPCODE_FLR, /* X X 2 X X */ OPCODE_FRC, /* X X 2 X X */ OPCODE_IF, /* opt */ - OPCODE_KIL, /* X */ + OPCODE_KIL, /* X X */ OPCODE_KIL_NV, /* X X */ OPCODE_LG2, /* X X 2 X X */ OPCODE_LIT, /* X X X X */ - OPCODE_LOG, /* X X X */ - OPCODE_LRP, /* X X X */ + OPCODE_LOG, /* X X */ + OPCODE_LRP, /* X X */ OPCODE_MAD, /* X X X X X */ OPCODE_MAX, /* X X X X X */ OPCODE_MIN, /* X X X X X */ @@ -196,8 +196,8 @@ typedef enum prog_opcode { OPCODE_NOISE3, /* X */ OPCODE_NOISE4, /* X */ OPCODE_NOT, /* */ - OPCODE_NRM3, /* X */ - OPCODE_NRM4, /* X */ + OPCODE_NRM3, /* */ + OPCODE_NRM4, /* */ OPCODE_OR, /* */ OPCODE_PK2H, /* X */ OPCODE_PK2US, /* X */ @@ -209,10 +209,10 @@ typedef enum prog_opcode { OPCODE_PUSHA, /* 3 */ OPCODE_RCC, /* 1.1 */ OPCODE_RCP, /* X X X X X */ - OPCODE_RET, /* 2 2 X */ + OPCODE_RET, /* 2 2 opt */ OPCODE_RFL, /* X X */ OPCODE_RSQ, /* X X X X X */ - OPCODE_SCS, /* X */ + OPCODE_SCS, /* X X */ OPCODE_SEQ, /* 2 X X */ OPCODE_SFL, /* 2 X */ OPCODE_SGE, /* X X X X X */ @@ -221,10 +221,10 @@ typedef enum prog_opcode { OPCODE_SLE, /* 2 X X */ OPCODE_SLT, /* X X X X X */ OPCODE_SNE, /* 2 X X */ - OPCODE_SSG, /* 2 */ + OPCODE_SSG, /* 2 X */ OPCODE_STR, /* 2 X */ OPCODE_SUB, /* X X 1.1 X X */ - OPCODE_SWZ, /* X X */ + OPCODE_SWZ, /* X X X */ OPCODE_TEX, /* X 3 X X */ OPCODE_TXB, /* X 3 X */ OPCODE_TXD, /* X X */ @@ -238,7 +238,7 @@ typedef enum prog_opcode { OPCODE_UP4UB, /* X */ OPCODE_X2D, /* X */ OPCODE_XOR, /* */ - OPCODE_XPD, /* X X X */ + OPCODE_XPD, /* X X */ MAX_OPCODE } gl_inst_opcode; diff --git a/src/mesa/program/prog_statevars.c b/src/mesa/program/prog_statevars.c index d94d7fe5dfb..16f9690e865 100644 --- a/src/mesa/program/prog_statevars.c +++ b/src/mesa/program/prog_statevars.c @@ -459,7 +459,7 @@ _mesa_fetch_state(struct gl_context *ctx, const gl_state_index state[], value[0] = (ctx->Fog.End == ctx->Fog.Start) ? 1.0f : (GLfloat)(-1.0F / (ctx->Fog.End - ctx->Fog.Start)); value[1] = ctx->Fog.End * -value[0]; - value[2] = (GLfloat)(ctx->Fog.Density * ONE_DIV_LN2); + value[2] = (GLfloat)(ctx->Fog.Density * M_LOG2E); /* M_LOG2E == 1/ln(2) */ value[3] = (GLfloat)(ctx->Fog.Density * ONE_DIV_SQRT_LN2); return; diff --git a/src/mesa/program/programopt.c b/src/mesa/program/programopt.c index a239da2c609..c72dfb23b4d 100644 --- a/src/mesa/program/programopt.c +++ b/src/mesa/program/programopt.c @@ -267,6 +267,11 @@ _mesa_append_fog_code(struct gl_context *ctx, return; } + if (!(fprog->Base.OutputsWritten & (1 << FRAG_RESULT_COLOR))) { + /* program doesn't output color, so nothing to do */ + return; + } + /* Alloc storage for new instructions */ newInst = _mesa_alloc_instructions(newLen); if (!newInst) { @@ -407,6 +412,7 @@ _mesa_append_fog_code(struct gl_context *ctx, fprog->Base.Instructions = newInst; fprog->Base.NumInstructions = inst - newInst; fprog->Base.InputsRead |= FRAG_BIT_FOGC; + assert(fprog->Base.OutputsWritten & (1 << FRAG_RESULT_COLOR)); } diff --git a/src/mesa/state_tracker/st_cb_drawpixels.c b/src/mesa/state_tracker/st_cb_drawpixels.c index e377861b8d2..9948f8d2bc5 100644 --- a/src/mesa/state_tracker/st_cb_drawpixels.c +++ b/src/mesa/state_tracker/st_cb_drawpixels.c @@ -39,6 +39,7 @@ #include "main/pack.h" #include "main/pbo.h" #include "main/texformat.h" +#include "main/teximage.h" #include "main/texstore.h" #include "program/program.h" #include "program/prog_print.h" @@ -419,10 +420,10 @@ make_texture(struct st_context *st, gl_format mformat; struct pipe_resource *pt; enum pipe_format pipeFormat; - GLenum baseFormat, intFormat; + GLenum baseInternalFormat, intFormat; - baseFormat = base_format(format); intFormat = internal_format(ctx, format, type); + baseInternalFormat = _mesa_base_tex_format(ctx, intFormat); mformat = st_ChooseTextureFormat_renderable(ctx, intFormat, format, type, GL_FALSE); @@ -465,7 +466,7 @@ make_texture(struct st_context *st, * the texture. We deal with that with texcoords. */ success = _mesa_texstore(ctx, 2, /* dims */ - baseFormat, /* baseInternalFormat */ + baseInternalFormat, /* baseInternalFormat */ mformat, /* gl_format */ dest, /* dest */ 0, 0, 0, /* dstX/Y/Zoffset */ diff --git a/src/mesa/state_tracker/st_extensions.c b/src/mesa/state_tracker/st_extensions.c index ad8e6bb9ec9..d3aebe526dd 100644 --- a/src/mesa/state_tracker/st_extensions.c +++ b/src/mesa/state_tracker/st_extensions.c @@ -603,4 +603,8 @@ void st_init_extensions(struct st_context *st) else if (screen->get_param(screen, PIPE_CAP_SEAMLESS_CUBE_MAP)) { ctx->Extensions.ARB_seamless_cube_map = GL_TRUE; } + + if (screen->get_param(screen, PIPE_CAP_SM3)) { + ctx->Extensions.ARB_shader_texture_lod = GL_TRUE; + } } |