diff options
| author | Marek Olšák <[email protected]> | 2015-09-06 15:43:23 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2015-10-07 19:18:50 +0200 |
| commit | 5749676d03d1a4964888a2d9a7624d3b96cc4886 (patch) | |
| tree | 081f8f1a6523ec619490d61898717e9af6c90249 | |
| parent | 6ed8fd3d6703bc51378e05a0e209df58d9844082 (diff) | |
radeonsi: remove TC L2 cache flush for index buffers on VI
Reviewed-by: Alex Deucher <[email protected]>
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_draw.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 43170ec446b..5face423941 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -813,9 +813,9 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info) } } - /* TODO: VI should read index buffers through TC, so this shouldn't be - * needed on VI. */ - if (info->indexed && r600_resource(ib.buffer)->TC_L2_dirty) { + /* VI reads index buffers through TC L2. */ + if (info->indexed && sctx->b.chip_class <= CIK && + r600_resource(ib.buffer)->TC_L2_dirty) { sctx->b.flags |= SI_CONTEXT_INV_TC_L2; r600_resource(ib.buffer)->TC_L2_dirty = false; } |