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authorJordan Justen <[email protected]>2014-07-08 18:17:57 +0000
committerBen Widawsky <[email protected]>2016-02-02 15:44:18 -0800
commit141ef75569aa9ffe392f19d7a375bbadebfd08be (patch)
tree73b44db0b32eb9349c7b607720dfe3cf76536980
parent18f688d62a69501072d6783bbce34d1a755ef2c9 (diff)
i965/gen8: Initialize aux_mode to GEN8_SURFACE_AUX_MODE_NONE
GEN8_SURFACE_AUX_MODE_NONE is 0, so this is a no-op. Yet, this also makes it clear that we can compare aux_mode to the other GEN8_SURFACE_AUX_MODE_ values. We will want to compare to GEN8_SURFACE_AUX_MODE_HIZ. v2: Some very minor cherry-pick conflicts due to moving it around in the series. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Ben Widawsky <[email protected]> Signed-off-by: Ben Widawsky <[email protected]>
-rw-r--r--src/mesa/drivers/dri/i965/gen8_surface_state.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index 904950dfa07..0df25d2557c 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -210,7 +210,7 @@ gen8_emit_texture_surface_state(struct brw_context *brw,
{
const unsigned depth = max_layer - min_layer;
struct intel_mipmap_tree *aux_mt = NULL;
- uint32_t aux_mode = 0;
+ uint32_t aux_mode = GEN8_SURFACE_AUX_MODE_NONE;
uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
int surf_index = surf_offset - &brw->wm.base.surf_offset[0];
unsigned tiling_mode, pitch;
@@ -425,7 +425,7 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
struct intel_mipmap_tree *mt = irb->mt;
struct intel_mipmap_tree *aux_mt = NULL;
- uint32_t aux_mode = 0;
+ uint32_t aux_mode = GEN8_SURFACE_AUX_MODE_NONE;
unsigned width = mt->logical_width0;
unsigned height = mt->logical_height0;
unsigned pitch = mt->pitch;