diff options
| author | Kenneth Graunke <[email protected]> | 2011-09-24 01:45:18 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2012-03-30 14:39:21 -0700 |
| commit | fc8edbe016348a22e4631fb1e1c7f7b87301c5ec (patch) | |
| tree | d060a40b7b573965c43f2e3502378d217b248a4a | |
| parent | b4410ac3944ee30bbf5455e3e649b73f559a7d38 (diff) | |
i965: Set "Stencil Buffer Enable" bit on Haswell.
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 1 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_misc_state.c | 5 |
2 files changed, 5 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index a0931121475..e7326c6ca3f 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1445,6 +1445,7 @@ enum brw_wm_barycentric_interp_mode { #define GEN7_3DSTATE_CLEAR_PARAMS 0x7804 #define GEN7_3DSTATE_DEPTH_BUFFER 0x7805 #define GEN7_3DSTATE_STENCIL_BUFFER 0x7806 +# define HSW_STENCIL_ENABLED (1 << 31) #define GEN7_3DSTATE_HIER_DEPTH_BUFFER 0x7807 #define _3DSTATE_CLEAR_PARAMS 0x7910 /* ILK, SNB */ diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c index d0ce54241b6..5da64349e5a 100644 --- a/src/mesa/drivers/dri/i965/gen7_misc_state.c +++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c @@ -139,9 +139,12 @@ static void emit_depthbuffer(struct brw_context *brw) OUT_BATCH(0); ADVANCE_BATCH(); } else { + const int enabled = intel->is_haswell ? HSW_STENCIL_ENABLED : 0; + BEGIN_BATCH(3); OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2)); - OUT_BATCH(stencil_mt->region->pitch * stencil_mt->region->cpp - 1); + OUT_BATCH(enabled | + (stencil_mt->region->pitch * stencil_mt->region->cpp - 1)); OUT_RELOC(stencil_mt->region->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); |