nvc0: rename NVXX_COMPUTE to NVXX_CP

Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Ilia Mirkin <[email protected]>

5 files changed, 117 insertions, 117 deletions

diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c b/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
index 26304ad2134..3f7a7d38ffc 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
@@ -59,60 +59,60 @@ nvc0_screen_compute_setup(struct nvc0_screen *screen,
    if (ret)
       return ret;
 
-   BEGIN_NVC0(push, SUBC_COMPUTE(NV01_SUBCHAN_OBJECT), 1);
+   BEGIN_NVC0(push, SUBC_CP(NV01_SUBCHAN_OBJECT), 1);
    PUSH_DATA (push, screen->compute->oclass);
 
    /* hardware limit */
-   BEGIN_NVC0(push, NVC0_COMPUTE(MP_LIMIT), 1);
+   BEGIN_NVC0(push, NVC0_CP(MP_LIMIT), 1);
    PUSH_DATA (push, screen->mp_count);
-   BEGIN_NVC0(push, NVC0_COMPUTE(CALL_LIMIT_LOG), 1);
+   BEGIN_NVC0(push, NVC0_CP(CALL_LIMIT_LOG), 1);
    PUSH_DATA (push, 0xf);
 
-   BEGIN_NVC0(push, SUBC_COMPUTE(0x02a0), 1);
+   BEGIN_NVC0(push, SUBC_CP(0x02a0), 1);
    PUSH_DATA (push, 0x8000);
 
    /* global memory setup */
-   BEGIN_NVC0(push, SUBC_COMPUTE(0x02c4), 1);
+   BEGIN_NVC0(push, SUBC_CP(0x02c4), 1);
    PUSH_DATA (push, 0);
-   BEGIN_NIC0(push, NVC0_COMPUTE(GLOBAL_BASE), 0x100);
+   BEGIN_NIC0(push, NVC0_CP(GLOBAL_BASE), 0x100);
    for (i = 0; i <= 0xff; i++)
       PUSH_DATA (push, (0xc << 28) | (i << 16) | i);
-   BEGIN_NVC0(push, SUBC_COMPUTE(0x02c4), 1);
+   BEGIN_NVC0(push, SUBC_CP(0x02c4), 1);
    PUSH_DATA (push, 1);
 
    /* local memory and cstack setup */
-   BEGIN_NVC0(push, NVC0_COMPUTE(TEMP_ADDRESS_HIGH), 2);
+   BEGIN_NVC0(push, NVC0_CP(TEMP_ADDRESS_HIGH), 2);
    PUSH_DATAh(push, screen->tls->offset);
    PUSH_DATA (push, screen->tls->offset);
-   BEGIN_NVC0(push, NVC0_COMPUTE(TEMP_SIZE_HIGH), 2);
+   BEGIN_NVC0(push, NVC0_CP(TEMP_SIZE_HIGH), 2);
    PUSH_DATAh(push, screen->tls->size);
    PUSH_DATA (push, screen->tls->size);
-   BEGIN_NVC0(push, NVC0_COMPUTE(WARP_TEMP_ALLOC), 1);
+   BEGIN_NVC0(push, NVC0_CP(WARP_TEMP_ALLOC), 1);
    PUSH_DATA (push, 0);
-   BEGIN_NVC0(push, NVC0_COMPUTE(LOCAL_BASE), 1);
+   BEGIN_NVC0(push, NVC0_CP(LOCAL_BASE), 1);
    PUSH_DATA (push, 0xff << 24);
 
    /* shared memory setup */
-   BEGIN_NVC0(push, NVC0_COMPUTE(CACHE_SPLIT), 1);
+   BEGIN_NVC0(push, NVC0_CP(CACHE_SPLIT), 1);
    PUSH_DATA (push, NVC0_COMPUTE_CACHE_SPLIT_48K_SHARED_16K_L1);
-   BEGIN_NVC0(push, NVC0_COMPUTE(SHARED_BASE), 1);
+   BEGIN_NVC0(push, NVC0_CP(SHARED_BASE), 1);
    PUSH_DATA (push, 0xfe << 24);
-   BEGIN_NVC0(push, NVC0_COMPUTE(SHARED_SIZE), 1);
+   BEGIN_NVC0(push, NVC0_CP(SHARED_SIZE), 1);
    PUSH_DATA (push, 0);
 
    /* code segment setup */
-   BEGIN_NVC0(push, NVC0_COMPUTE(CODE_ADDRESS_HIGH), 2);
+   BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
    PUSH_DATAh(push, screen->text->offset);
    PUSH_DATA (push, screen->text->offset);
 
    /* textures */
-   BEGIN_NVC0(push, NVC0_COMPUTE(TIC_ADDRESS_HIGH), 3);
+   BEGIN_NVC0(push, NVC0_CP(TIC_ADDRESS_HIGH), 3);
    PUSH_DATAh(push, screen->txc->offset);
    PUSH_DATA (push, screen->txc->offset);
    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
 
    /* samplers */
-   BEGIN_NVC0(push, NVC0_COMPUTE(TSC_ADDRESS_HIGH), 3);
+   BEGIN_NVC0(push, NVC0_CP(TSC_ADDRESS_HIGH), 3);
    PUSH_DATAh(push, screen->txc->offset + 65536);
    PUSH_DATA (push, screen->txc->offset + 65536);
    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
@@ -140,7 +140,7 @@ nvc0_compute_validate_program(struct nvc0_context *nvc0)
    if (likely(prog->code_size)) {
       if (nvc0_program_upload_code(nvc0, prog)) {
          struct nouveau_pushbuf *push = nvc0->base.pushbuf;
-         BEGIN_NVC0(push, NVC0_COMPUTE(FLUSH), 1);
+         BEGIN_NVC0(push, NVC0_CP(FLUSH), 1);
          PUSH_DATA (push, NVC0_COMPUTE_FLUSH_CODE);
          return true;
       }
@@ -153,7 +153,7 @@ nvc0_compute_validate_samplers(struct nvc0_context *nvc0)
 {
    bool need_flush = nvc0_validate_tsc(nvc0, 5);
    if (need_flush) {
-      BEGIN_NVC0(nvc0->base.pushbuf, NVC0_COMPUTE(TSC_FLUSH), 1);
+      BEGIN_NVC0(nvc0->base.pushbuf, NVC0_CP(TSC_FLUSH), 1);
       PUSH_DATA (nvc0->base.pushbuf, 0);
    }
 }
@@ -163,7 +163,7 @@ nvc0_compute_validate_textures(struct nvc0_context *nvc0)
 {
    bool need_flush = nvc0_validate_tic(nvc0, 5);
    if (need_flush) {
-      BEGIN_NVC0(nvc0->base.pushbuf, NVC0_COMPUTE(TIC_FLUSH), 1);
+      BEGIN_NVC0(nvc0->base.pushbuf, NVC0_CP(TIC_FLUSH), 1);
       PUSH_DATA (nvc0->base.pushbuf, 0);
    }
 }
@@ -188,11 +188,11 @@ nvc0_compute_validate_constbufs(struct nvc0_context *nvc0)
          if (nvc0->state.uniform_buffer_bound[s] < size) {
             nvc0->state.uniform_buffer_bound[s] = align(size, 0x100);
 
-            BEGIN_NVC0(push, NVC0_COMPUTE(CB_SIZE), 3);
+            BEGIN_NVC0(push, NVC0_CP(CB_SIZE), 3);
             PUSH_DATA (push, nvc0->state.uniform_buffer_bound[s]);
             PUSH_DATAh(push, bo->offset + base);
             PUSH_DATA (push, bo->offset + base);
-            BEGIN_NVC0(push, NVC0_COMPUTE(CB_BIND), 1);
+            BEGIN_NVC0(push, NVC0_CP(CB_BIND), 1);
             PUSH_DATA (push, (0 << 8) | 1);
          }
          nvc0_cb_bo_push(&nvc0->base, bo, NV_VRAM_DOMAIN(&nvc0->screen->base),
@@ -203,18 +203,18 @@ nvc0_compute_validate_constbufs(struct nvc0_context *nvc0)
          struct nv04_resource *res =
             nv04_resource(nvc0->constbuf[s][i].u.buf);
          if (res) {
-            BEGIN_NVC0(push, NVC0_COMPUTE(CB_SIZE), 3);
+            BEGIN_NVC0(push, NVC0_CP(CB_SIZE), 3);
             PUSH_DATA (push, nvc0->constbuf[s][i].size);
             PUSH_DATAh(push, res->address + nvc0->constbuf[s][i].offset);
             PUSH_DATA (push, res->address + nvc0->constbuf[s][i].offset);
-            BEGIN_NVC0(push, NVC0_COMPUTE(CB_BIND), 1);
+            BEGIN_NVC0(push, NVC0_CP(CB_BIND), 1);
             PUSH_DATA (push, (i << 8) | 1);
 
             BCTX_REFN(nvc0->bufctx_cp, CP_CB(i), res, RD);
 
             res->cb_bindings[s] |= 1 << i;
          } else {
-            BEGIN_NVC0(push, NVC0_COMPUTE(CB_BIND), 1);
+            BEGIN_NVC0(push, NVC0_CP(CB_BIND), 1);
             PUSH_DATA (push, (i << 8) | 0);
          }
          if (i == 0)
@@ -222,7 +222,7 @@ nvc0_compute_validate_constbufs(struct nvc0_context *nvc0)
       }
    }
 
-   BEGIN_NVC0(push, NVC0_COMPUTE(FLUSH), 1);
+   BEGIN_NVC0(push, NVC0_CP(FLUSH), 1);
    PUSH_DATA (push, NVC0_COMPUTE_FLUSH_CB);
 }
 
@@ -232,11 +232,11 @@ nvc0_compute_validate_driverconst(struct nvc0_context *nvc0)
    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
    struct nvc0_screen *screen = nvc0->screen;
 
-   BEGIN_NVC0(push, NVC0_COMPUTE(CB_SIZE), 3);
+   BEGIN_NVC0(push, NVC0_CP(CB_SIZE), 3);
    PUSH_DATA (push, 1024);
    PUSH_DATAh(push, screen->uniform_bo->offset + (6 << 16) + (5 << 10));
    PUSH_DATA (push, screen->uniform_bo->offset + (6 << 16) + (5 << 10));
-   BEGIN_NVC0(push, NVC0_COMPUTE(CB_BIND), 1);
+   BEGIN_NVC0(push, NVC0_CP(CB_BIND), 1);
    PUSH_DATA (push, (15 << 8) | 1);
 
    nvc0->dirty_3d |= NVC0_NEW_DRIVERCONST;
@@ -249,11 +249,11 @@ nvc0_compute_validate_buffers(struct nvc0_context *nvc0)
    const int s = 5;
    int i;
 
-   BEGIN_NVC0(push, NVC0_COMPUTE(CB_SIZE), 3);
+   BEGIN_NVC0(push, NVC0_CP(CB_SIZE), 3);
    PUSH_DATA (push, 1024);
    PUSH_DATAh(push, nvc0->screen->uniform_bo->offset + (6 << 16) + (s << 10));
    PUSH_DATA (push, nvc0->screen->uniform_bo->offset + (6 << 16) + (s << 10));
-   BEGIN_1IC0(push, NVC0_COMPUTE(CB_POS), 1 + 4 * NVC0_MAX_BUFFERS);
+   BEGIN_1IC0(push, NVC0_CP(CB_POS), 1 + 4 * NVC0_MAX_BUFFERS);
    PUSH_DATA (push, 512);
 
    for (i = 0; i < NVC0_MAX_BUFFERS; i++) {
@@ -312,18 +312,18 @@ nvc0_compute_upload_input(struct nvc0_context *nvc0, const void *input)
    struct nvc0_program *cp = nvc0->compprog;
 
    if (cp->parm_size) {
-      BEGIN_NVC0(push, NVC0_COMPUTE(CB_SIZE), 3);
+      BEGIN_NVC0(push, NVC0_CP(CB_SIZE), 3);
       PUSH_DATA (push, align(cp->parm_size, 0x100));
       PUSH_DATAh(push, screen->parm->offset);
       PUSH_DATA (push, screen->parm->offset);
-      BEGIN_NVC0(push, NVC0_COMPUTE(CB_BIND), 1);
+      BEGIN_NVC0(push, NVC0_CP(CB_BIND), 1);
       PUSH_DATA (push, (0 << 8) | 1);
       /* NOTE: size is limited to 4 KiB, which is < NV04_PFIFO_MAX_PACKET_LEN */
-      BEGIN_1IC0(push, NVC0_COMPUTE(CB_POS), 1 + cp->parm_size / 4);
+      BEGIN_1IC0(push, NVC0_CP(CB_POS), 1 + cp->parm_size / 4);
       PUSH_DATA (push, 0);
       PUSH_DATAp(push, input, cp->parm_size / 4);
 
-      BEGIN_NVC0(push, NVC0_COMPUTE(FLUSH), 1);
+      BEGIN_NVC0(push, NVC0_CP(FLUSH), 1);
       PUSH_DATA (push, NVC0_COMPUTE_FLUSH_CB);
    }
 }
@@ -345,31 +345,31 @@ nvc0_launch_grid(struct pipe_context *pipe, const struct pipe_grid_info *info)
 
    nvc0_compute_upload_input(nvc0, info->input);
 
-   BEGIN_NVC0(push, NVC0_COMPUTE(CP_START_ID), 1);
+   BEGIN_NVC0(push, NVC0_CP(CP_START_ID), 1);
    PUSH_DATA (push, nvc0_program_symbol_offset(cp, info->pc));
 
-   BEGIN_NVC0(push, NVC0_COMPUTE(LOCAL_POS_ALLOC), 3);
+   BEGIN_NVC0(push, NVC0_CP(LOCAL_POS_ALLOC), 3);
    PUSH_DATA (push, align(cp->cp.lmem_size, 0x10));
    PUSH_DATA (push, 0);
    PUSH_DATA (push, 0x800); /* WARP_CSTACK_SIZE */
 
-   BEGIN_NVC0(push, NVC0_COMPUTE(SHARED_SIZE), 3);
+   BEGIN_NVC0(push, NVC0_CP(SHARED_SIZE), 3);
    PUSH_DATA (push, align(cp->cp.smem_size, 0x100));
    PUSH_DATA (push, info->block[0] * info->block[1] * info->block[2]);
    PUSH_DATA (push, cp->num_barriers);
-   BEGIN_NVC0(push, NVC0_COMPUTE(CP_GPR_ALLOC), 1);
+   BEGIN_NVC0(push, NVC0_CP(CP_GPR_ALLOC), 1);
    PUSH_DATA (push, cp->num_gprs);
 
    /* launch preliminary setup */
-   BEGIN_NVC0(push, NVC0_COMPUTE(GRIDID), 1);
+   BEGIN_NVC0(push, NVC0_CP(GRIDID), 1);
    PUSH_DATA (push, 0x1);
-   BEGIN_NVC0(push, SUBC_COMPUTE(0x036c), 1);
+   BEGIN_NVC0(push, SUBC_CP(0x036c), 1);
    PUSH_DATA (push, 0);
-   BEGIN_NVC0(push, NVC0_COMPUTE(FLUSH), 1);
+   BEGIN_NVC0(push, NVC0_CP(FLUSH), 1);
    PUSH_DATA (push, NVC0_COMPUTE_FLUSH_GLOBAL | NVC0_COMPUTE_FLUSH_UNK8);
 
    /* block setup */
-   BEGIN_NVC0(push, NVC0_COMPUTE(BLOCKDIM_YX), 2);
+   BEGIN_NVC0(push, NVC0_CP(BLOCKDIM_YX), 2);
    PUSH_DATA (push, (info->block[1] << 16) | info->block[0]);
    PUSH_DATA (push, info->block[2]);
 
@@ -385,20 +385,20 @@ nvc0_launch_grid(struct pipe_context *pipe, const struct pipe_grid_info *info)
                            NVC0_IB_ENTRY_1_NO_PREFETCH | 3 * 4);
    } else {
       /* grid setup */
-      BEGIN_NVC0(push, NVC0_COMPUTE(GRIDDIM_YX), 2);
+      BEGIN_NVC0(push, NVC0_CP(GRIDDIM_YX), 2);
       PUSH_DATA (push, (info->grid[1] << 16) | info->grid[0]);
       PUSH_DATA (push, info->grid[2]);
 
       /* kernel launching */
-      BEGIN_NVC0(push, NVC0_COMPUTE(COMPUTE_BEGIN), 1);
+      BEGIN_NVC0(push, NVC0_CP(COMPUTE_BEGIN), 1);
       PUSH_DATA (push, 0);
-      BEGIN_NVC0(push, SUBC_COMPUTE(0x0a08), 1);
+      BEGIN_NVC0(push, SUBC_CP(0x0a08), 1);
       PUSH_DATA (push, 0);
-      BEGIN_NVC0(push, NVC0_COMPUTE(LAUNCH), 1);
+      BEGIN_NVC0(push, NVC0_CP(LAUNCH), 1);
       PUSH_DATA (push, 0x1000);
-      BEGIN_NVC0(push, NVC0_COMPUTE(COMPUTE_END), 1);
+      BEGIN_NVC0(push, NVC0_CP(COMPUTE_END), 1);
       PUSH_DATA (push, 0);
-      BEGIN_NVC0(push, SUBC_COMPUTE(0x0360), 1);
+      BEGIN_NVC0(push, SUBC_CP(0x0360), 1);
       PUSH_DATA (push, 0x1);
    }
 
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c
index 68c8ff53ae6..f5f9bb39fd9 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c
@@ -846,15 +846,15 @@ nve4_hw_sm_begin_query(struct nvc0_context *nvc0, struct nvc0_hw_query *hq)
 
       /* configure and reset the counter(s) */
      if (d == 0)
-        BEGIN_NVC0(push, NVE4_COMPUTE(MP_PM_A_SIGSEL(c & 3)), 1);
+        BEGIN_NVC0(push, NVE4_CP(MP_PM_A_SIGSEL(c & 3)), 1);
      else
-        BEGIN_NVC0(push, NVE4_COMPUTE(MP_PM_B_SIGSEL(c & 3)), 1);
+        BEGIN_NVC0(push, NVE4_CP(MP_PM_B_SIGSEL(c & 3)), 1);
      PUSH_DATA (push, cfg->ctr[i].sig_sel);
-     BEGIN_NVC0(push, NVE4_COMPUTE(MP_PM_SRCSEL(c)), 1);
+     BEGIN_NVC0(push, NVE4_CP(MP_PM_SRCSEL(c)), 1);
      PUSH_DATA (push, cfg->ctr[i].src_sel + 0x2108421 * (c & 3));
-     BEGIN_NVC0(push, NVE4_COMPUTE(MP_PM_FUNC(c)), 1);
+     BEGIN_NVC0(push, NVE4_CP(MP_PM_FUNC(c)), 1);
      PUSH_DATA (push, (cfg->ctr[i].func << 4) | cfg->ctr[i].mode);
-     BEGIN_NVC0(push, NVE4_COMPUTE(MP_PM_SET(c)), 1);
+     BEGIN_NVC0(push, NVE4_CP(MP_PM_SET(c)), 1);
      PUSH_DATA (push, 0);
    }
    return true;
@@ -917,13 +917,13 @@ nvc0_hw_sm_begin_query(struct nvc0_context *nvc0, struct nvc0_hw_query *hq)
       mask_sel &= cfg->ctr[i].src_mask;
 
       /* configure and reset the counter(s) */
-      BEGIN_NVC0(push, NVC0_COMPUTE(MP_PM_SIGSEL(c)), 1);
+      BEGIN_NVC0(push, NVC0_CP(MP_PM_SIGSEL(c)), 1);
       PUSH_DATA (push, cfg->ctr[i].sig_sel);
-      BEGIN_NVC0(push, NVC0_COMPUTE(MP_PM_SRCSEL(c)), 1);
+      BEGIN_NVC0(push, NVC0_CP(MP_PM_SRCSEL(c)), 1);
       PUSH_DATA (push, cfg->ctr[i].src_sel | mask_sel);
-      BEGIN_NVC0(push, NVC0_COMPUTE(MP_PM_OP(c)), 1);
+      BEGIN_NVC0(push, NVC0_CP(MP_PM_OP(c)), 1);
       PUSH_DATA (push, (cfg->ctr[i].func << 4) | cfg->ctr[i].mode);
-      BEGIN_NVC0(push, NVC0_COMPUTE(MP_PM_SET(c)), 1);
+      BEGIN_NVC0(push, NVC0_CP(MP_PM_SET(c)), 1);
       PUSH_DATA (push, 0);
    }
    return true;
@@ -966,9 +966,9 @@ nvc0_hw_sm_end_query(struct nvc0_context *nvc0, struct nvc0_hw_query *hq)
    for (c = 0; c < 8; ++c)
       if (screen->pm.mp_counter[c]) {
          if (is_nve4) {
-            IMMED_NVC0(push, NVE4_COMPUTE(MP_PM_FUNC(c)), 0);
+            IMMED_NVC0(push, NVE4_CP(MP_PM_FUNC(c)), 0);
          } else {
-            IMMED_NVC0(push, NVC0_COMPUTE(MP_PM_OP(c)), 0);
+            IMMED_NVC0(push, NVC0_CP(MP_PM_OP(c)), 0);
          }
       }
    /* release counters for this query */
@@ -984,7 +984,7 @@ nvc0_hw_sm_end_query(struct nvc0_context *nvc0, struct nvc0_hw_query *hq)
                 hq->bo);
 
    PUSH_SPACE(push, 1);
-   IMMED_NVC0(push, SUBC_COMPUTE(NV50_GRAPH_SERIALIZE), 0);
+   IMMED_NVC0(push, SUBC_CP(NV50_GRAPH_SERIALIZE), 0);
 
    pipe->bind_compute_state(pipe, screen->pm.prog);
    input[0] = (hq->bo->offset + hq->base_offset);
@@ -1018,9 +1018,9 @@ nvc0_hw_sm_end_query(struct nvc0_context *nvc0, struct nvc0_hw_query *hq)
             break;
          mask |= 1 << hsq->ctr[i];
          if (is_nve4) {
-            BEGIN_NVC0(push, NVE4_COMPUTE(MP_PM_FUNC(hsq->ctr[i])), 1);
+            BEGIN_NVC0(push, NVE4_CP(MP_PM_FUNC(hsq->ctr[i])), 1);
          } else {
-            BEGIN_NVC0(push, NVC0_COMPUTE(MP_PM_OP(hsq->ctr[i])), 1);
+            BEGIN_NVC0(push, NVC0_CP(MP_PM_OP(hsq->ctr[i])), 1);
          }
          PUSH_DATA (push, (cfg->ctr[i].func << 4) | cfg->ctr[i].mode);
       }
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
index df10a742186..303cc58798c 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
@@ -472,7 +472,7 @@ nvc0_validate_tic(struct nvc0_context *nvc0, int s)
       } else
       if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
          if (unlikely(s == 5))
-            BEGIN_NVC0(push, NVC0_COMPUTE(TEX_CACHE_CTL), 1);
+            BEGIN_NVC0(push, NVC0_CP(TEX_CACHE_CTL), 1);
          else
             BEGIN_NVC0(push, NVC0_3D(TEX_CACHE_CTL), 1);
          PUSH_DATA (push, (tic->id << 4) | 1);
@@ -499,7 +499,7 @@ nvc0_validate_tic(struct nvc0_context *nvc0, int s)
 
    if (n) {
       if (unlikely(s == 5))
-         BEGIN_NIC0(push, NVC0_COMPUTE(BIND_TIC), n);
+         BEGIN_NIC0(push, NVC0_CP(BIND_TIC), n);
       else
          BEGIN_NIC0(push, NVC0_3D(BIND_TIC(s)), n);
       PUSH_DATAp(push, commands, n);
@@ -625,7 +625,7 @@ nvc0_validate_tsc(struct nvc0_context *nvc0, int s)
 
    if (n) {
       if (unlikely(s == 5))
-         BEGIN_NIC0(push, NVC0_COMPUTE(BIND_TSC), n);
+         BEGIN_NIC0(push, NVC0_CP(BIND_TSC), n);
       else
          BEGIN_NIC0(push, NVC0_3D(BIND_TSC(s)), n);
       PUSH_DATAp(push, commands, n);
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_winsys.h b/src/gallium/drivers/nouveau/nvc0/nvc0_winsys.h
index 79abe78b77a..4d07546c310 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_winsys.h
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_winsys.h
@@ -50,9 +50,9 @@ PUSH_REFN(struct nouveau_pushbuf *push, struct nouveau_bo *bo, uint32_t flags)
 #define NVC0_3D(n) SUBC_3D(NVC0_3D_##n)
 #define NVE4_3D(n) SUBC_3D(NVE4_3D_##n)
 
-#define SUBC_COMPUTE(m) 1, (m)
-#define NVC0_COMPUTE(n) SUBC_COMPUTE(NVC0_COMPUTE_##n)
-#define NVE4_COMPUTE(n) SUBC_COMPUTE(NVE4_COMPUTE_##n)
+#define SUBC_CP(m) 1, (m)
+#define NVC0_CP(n) SUBC_CP(NVC0_COMPUTE_##n)
+#define NVE4_CP(n) SUBC_CP(NVE4_COMPUTE_##n)
 
 #define SUBC_M2MF(m) 2, (m)
 #define SUBC_P2MF(m) 2, (m)
diff --git a/src/gallium/drivers/nouveau/nvc0/nve4_compute.c b/src/gallium/drivers/nouveau/nvc0/nve4_compute.c
index c741616458c..652bc6d83d6 100644
--- a/src/gallium/drivers/nouveau/nvc0/nve4_compute.c
+++ b/src/gallium/drivers/nouveau/nvc0/nve4_compute.c
@@ -71,21 +71,21 @@ nve4_screen_compute_setup(struct nvc0_screen *screen,
    if (ret)
       return ret;
 
-   BEGIN_NVC0(push, SUBC_COMPUTE(NV01_SUBCHAN_OBJECT), 1);
+   BEGIN_NVC0(push, SUBC_CP(NV01_SUBCHAN_OBJECT), 1);
    PUSH_DATA (push, screen->compute->oclass);
 
-   BEGIN_NVC0(push, NVE4_COMPUTE(TEMP_ADDRESS_HIGH), 2);
+   BEGIN_NVC0(push, NVE4_CP(TEMP_ADDRESS_HIGH), 2);
    PUSH_DATAh(push, screen->tls->offset);
    PUSH_DATA (push, screen->tls->offset);
    /* No idea why there are 2. Divide size by 2 to be safe.
     * Actually this might be per-MP TEMP size and looks like I'm only using
     * 2 MPs instead of all 8.
     */
-   BEGIN_NVC0(push, NVE4_COMPUTE(MP_TEMP_SIZE_HIGH(0)), 3);
+   BEGIN_NVC0(push, NVE4_CP(MP_TEMP_SIZE_HIGH(0)), 3);
    PUSH_DATAh(push, screen->tls->size / screen->mp_count);
    PUSH_DATA (push, (screen->tls->size / screen->mp_count) & ~0x7fff);
    PUSH_DATA (push, 0xff);
-   BEGIN_NVC0(push, NVE4_COMPUTE(MP_TEMP_SIZE_HIGH(1)), 3);
+   BEGIN_NVC0(push, NVE4_CP(MP_TEMP_SIZE_HIGH(1)), 3);
    PUSH_DATAh(push, screen->tls->size / screen->mp_count);
    PUSH_DATA (push, (screen->tls->size / screen->mp_count) & ~0x7fff);
    PUSH_DATA (push, 0xff);
@@ -95,24 +95,24 @@ nve4_screen_compute_setup(struct nvc0_screen *screen,
     * FATAL: Buffers with addresses inside [0x1000000, 0x3000000] will NOT be
     *  accessible. We cannot prevent that at the moment, so expect failure.
     */
-   BEGIN_NVC0(push, NVE4_COMPUTE(LOCAL_BASE), 1);
+   BEGIN_NVC0(push, NVE4_CP(LOCAL_BASE), 1);
    PUSH_DATA (push, 1 << 24);
-   BEGIN_NVC0(push, NVE4_COMPUTE(SHARED_BASE), 1);
+   BEGIN_NVC0(push, NVE4_CP(SHARED_BASE), 1);
    PUSH_DATA (push, 2 << 24);
 
-   BEGIN_NVC0(push, NVE4_COMPUTE(CODE_ADDRESS_HIGH), 2);
+   BEGIN_NVC0(push, NVE4_CP(CODE_ADDRESS_HIGH), 2);
    PUSH_DATAh(push, screen->text->offset);
    PUSH_DATA (push, screen->text->offset);
 
-   BEGIN_NVC0(push, SUBC_COMPUTE(0x0310), 1);
+   BEGIN_NVC0(push, SUBC_CP(0x0310), 1);
    PUSH_DATA (push, (obj_class >= NVF0_COMPUTE_CLASS) ? 0x400 : 0x300);
 
    /* NOTE: these do not affect the state used by the 3D object */
-   BEGIN_NVC0(push, NVE4_COMPUTE(TIC_ADDRESS_HIGH), 3);
+   BEGIN_NVC0(push, NVE4_CP(TIC_ADDRESS_HIGH), 3);
    PUSH_DATAh(push, screen->txc->offset);
    PUSH_DATA (push, screen->txc->offset);
    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
-   BEGIN_NVC0(push, NVE4_COMPUTE(TSC_ADDRESS_HIGH), 3);
+   BEGIN_NVC0(push, NVE4_CP(TSC_ADDRESS_HIGH), 3);
    PUSH_DATAh(push, screen->txc->offset + 65536);
    PUSH_DATA (push, screen->txc->offset + 65536);
    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
@@ -122,26 +122,26 @@ nve4_screen_compute_setup(struct nvc0_screen *screen,
        * passed with GK110_COMPUTE.GRAPH.SCRATCH[0x2]. This is currently
        * disabled because our firmware doesn't support these commands and the
        * GPU hangs if they are used. */
-      BEGIN_NIC0(push, SUBC_COMPUTE(0x0248), 64);
+      BEGIN_NIC0(push, SUBC_CP(0x0248), 64);
       for (i = 63; i >= 0; i--)
          PUSH_DATA(push, 0x38000 | i);
-      IMMED_NVC0(push, SUBC_COMPUTE(NV50_GRAPH_SERIALIZE), 0);
+      IMMED_NVC0(push, SUBC_CP(NV50_GRAPH_SERIALIZE), 0);
    }
 
-   BEGIN_NVC0(push, NVE4_COMPUTE(TEX_CB_INDEX), 1);
+   BEGIN_NVC0(push, NVE4_CP(TEX_CB_INDEX), 1);
    PUSH_DATA (push, 0); /* does not interefere with 3D */
 
    if (obj_class == NVF0_COMPUTE_CLASS)
-      IMMED_NVC0(push, SUBC_COMPUTE(0x02c4), 1);
+      IMMED_NVC0(push, SUBC_CP(0x02c4), 1);
 
    /* MS sample coordinate offsets: these do not work with _ALT modes ! */
-   BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2);
+   BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
    PUSH_DATAh(push, screen->parm->offset + NVE4_CP_INPUT_MS_OFFSETS);
    PUSH_DATA (push, screen->parm->offset + NVE4_CP_INPUT_MS_OFFSETS);
-   BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2);
+   BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
    PUSH_DATA (push, 64);
    PUSH_DATA (push, 1);
-   BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 17);
+   BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 17);
    PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
    PUSH_DATA (push, 0); /* 0 */
    PUSH_DATA (push, 0);
@@ -161,13 +161,13 @@ nve4_screen_compute_setup(struct nvc0_screen *screen,
    PUSH_DATA (push, 1);
 
 #ifdef DEBUG
-   BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2);
+   BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
    PUSH_DATAh(push, screen->parm->offset + NVE4_CP_INPUT_TRAP_INFO_PTR);
    PUSH_DATA (push, screen->parm->offset + NVE4_CP_INPUT_TRAP_INFO_PTR);
-   BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2);
+   BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
    PUSH_DATA (push, 28);
    PUSH_DATA (push, 1);
-   BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 8);
+   BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 8);
    PUSH_DATA (push, 1);
    PUSH_DATA (push, screen->parm->offset + NVE4_CP_PARAM_TRAP_INFO);
    PUSH_DATAh(push, screen->parm->offset + NVE4_CP_PARAM_TRAP_INFO);
@@ -178,7 +178,7 @@ nve4_screen_compute_setup(struct nvc0_screen *screen,
    PUSH_DATA (push, 0); /* warp cfstack size */
 #endif
 
-   BEGIN_NVC0(push, NVE4_COMPUTE(FLUSH), 1);
+   BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
    PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
 
    return 0;
@@ -205,13 +205,13 @@ nve4_compute_validate_surfaces(struct nvc0_context *nvc0)
        * NVE4's surface load/store instructions receive all the information
        * directly instead of via binding points, so we have to supply them.
        */
-      BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2);
+      BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
       PUSH_DATAh(push, screen->parm->offset + NVE4_CP_INPUT_SUF(i));
       PUSH_DATA (push, screen->parm->offset + NVE4_CP_INPUT_SUF(i));
-      BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2);
+      BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
       PUSH_DATA (push, 64);
       PUSH_DATA (push, 1);
-      BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 17);
+      BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 17);
       PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
 
       nve4_set_surface_info(push, nvc0->surfaces[t][i], screen);
@@ -227,7 +227,7 @@ nve4_compute_validate_surfaces(struct nvc0_context *nvc0)
       }
    }
    if (nvc0->surfaces_dirty[t]) {
-      BEGIN_NVC0(push, NVE4_COMPUTE(FLUSH), 1);
+      BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
       PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
    }
 
@@ -256,7 +256,7 @@ nve4_compute_validate_samplers(struct nvc0_context *nvc0)
 {
    bool need_flush = nve4_validate_tsc(nvc0, 5);
    if (need_flush) {
-      BEGIN_NVC0(nvc0->base.pushbuf, NVE4_COMPUTE(TSC_FLUSH), 1);
+      BEGIN_NVC0(nvc0->base.pushbuf, NVE4_CP(TSC_FLUSH), 1);
       PUSH_DATA (nvc0->base.pushbuf, 0);
    }
 }
@@ -285,17 +285,17 @@ nve4_compute_set_tex_handles(struct nvc0_context *nvc0)
 
    address = nvc0->screen->parm->offset + NVE4_CP_INPUT_TEX(i);
 
-   BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2);
+   BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
    PUSH_DATAh(push, address);
    PUSH_DATA (push, address);
-   BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2);
+   BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
    PUSH_DATA (push, n * 4);
    PUSH_DATA (push, 0x1);
-   BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 1 + n);
+   BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + n);
    PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
    PUSH_DATAp(push, &nvc0->tex_handles[s][i], n);
 
-   BEGIN_NVC0(push, NVE4_COMPUTE(FLUSH), 1);
+   BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
    PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
 
    nvc0->textures_dirty[s] = 0;
@@ -342,29 +342,29 @@ nve4_compute_upload_input(struct nvc0_context *nvc0, const void *input,
    struct nvc0_program *cp = nvc0->compprog;
 
    if (cp->parm_size) {
-      BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2);
+      BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
       PUSH_DATAh(push, screen->parm->offset);
       PUSH_DATA (push, screen->parm->offset);
-      BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2);
+      BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
       PUSH_DATA (push, cp->parm_size);
       PUSH_DATA (push, 0x1);
-      BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 1 + (cp->parm_size / 4));
+      BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + (cp->parm_size / 4));
       PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
       PUSH_DATAp(push, input, cp->parm_size / 4);
    }
-   BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2);
+   BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
    PUSH_DATAh(push, screen->parm->offset + NVE4_CP_INPUT_GRID_INFO(0));
    PUSH_DATA (push, screen->parm->offset + NVE4_CP_INPUT_GRID_INFO(0));
-   BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2);
+   BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
    PUSH_DATA (push, 7 * 4);
    PUSH_DATA (push, 0x1);
-   BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 1 + 7);
+   BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + 7);
    PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
    PUSH_DATAp(push, block_layout, 3);
    PUSH_DATAp(push, grid_layout, 3);
    PUSH_DATA (push, 0);
 
-   BEGIN_NVC0(push, NVE4_COMPUTE(FLUSH), 1);
+   BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
    PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
 }
 
@@ -465,23 +465,23 @@ nve4_launch_grid(struct pipe_context *pipe, const struct pipe_grid_info *info)
 
    /* upload descriptor and flush */
 #if 0
-   BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2);
+   BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
    PUSH_DATAh(push, desc_gpuaddr);
    PUSH_DATA (push, desc_gpuaddr);
-   BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2);
+   BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
    PUSH_DATA (push, 256);
    PUSH_DATA (push, 1);
-   BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 1 + (256 / 4));
+   BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + (256 / 4));
    PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x08 << 1));
    PUSH_DATAp(push, (const uint32_t *)desc, 256 / 4);
-   BEGIN_NVC0(push, NVE4_COMPUTE(FLUSH), 1);
+   BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
    PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB | NVE4_COMPUTE_FLUSH_CODE);
 #endif
-   BEGIN_NVC0(push, NVE4_COMPUTE(LAUNCH_DESC_ADDRESS), 1);
+   BEGIN_NVC0(push, NVE4_CP(LAUNCH_DESC_ADDRESS), 1);
    PUSH_DATA (push, desc_gpuaddr >> 8);
-   BEGIN_NVC0(push, NVE4_COMPUTE(LAUNCH), 1);
+   BEGIN_NVC0(push, NVE4_CP(LAUNCH), 1);
    PUSH_DATA (push, 0x3);
-   BEGIN_NVC0(push, SUBC_COMPUTE(NV50_GRAPH_SERIALIZE), 1);
+   BEGIN_NVC0(push, SUBC_CP(NV50_GRAPH_SERIALIZE), 1);
    PUSH_DATA (push, 0);
 
 out:
@@ -519,13 +519,13 @@ nve4_compute_validate_textures(struct nvc0_context *nvc0)
          tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic);
 
          PUSH_SPACE(push, 16);
-         BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2);
+         BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
          PUSH_DATAh(push, txc->offset + (tic->id * 32));
          PUSH_DATA (push, txc->offset + (tic->id * 32));
-         BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2);
+         BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
          PUSH_DATA (push, 32);
          PUSH_DATA (push, 1);
-         BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 9);
+         BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 9);
          PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
          PUSH_DATAp(push, &tic->tic[0], 8);
 
@@ -548,11 +548,11 @@ nve4_compute_validate_textures(struct nvc0_context *nvc0)
       nvc0->tex_handles[s][i] |= NVE4_TIC_ENTRY_INVALID;
 
    if (n[0]) {
-      BEGIN_NIC0(push, NVE4_COMPUTE(TIC_FLUSH), n[0]);
+      BEGIN_NIC0(push, NVE4_CP(TIC_FLUSH), n[0]);
       PUSH_DATAp(push, commands[0], n[0]);
    }
    if (n[1]) {
-      BEGIN_NIC0(push, NVE4_COMPUTE(TEX_CACHE_CTL), n[1]);
+      BEGIN_NIC0(push, NVE4_CP(TEX_CACHE_CTL), n[1]);
       PUSH_DATAp(push, commands[1], n[1]);
    }