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authorMatt Turner <[email protected]>2013-04-15 14:59:09 -0700
committerMatt Turner <[email protected]>2013-04-17 18:19:34 -0700
commit60e4c994884ac10954f341db13a4c9c410c4dd0e (patch)
treee800b2e64a8b7a220a7e04a5db12dc94901cb3d7
parent1a59cc777fb6c0383ed0c745000ca7409b1027d9 (diff)
i965: Implement work-around for CMP with null dest on Haswell.
Reviewed-by: Kenneth Graunke <[email protected]>
-rw-r--r--src/mesa/drivers/dri/i965/brw_eu_emit.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 2578bf89cca..704f219f6f7 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -1653,6 +1653,7 @@ void brw_CMP(struct brw_compile *p,
struct brw_reg src0,
struct brw_reg src1)
{
+ struct intel_context *intel = &p->brw->intel;
struct brw_instruction *insn = next_insn(p, BRW_OPCODE_CMP);
insn->header.destreg__conditionalmod = conditional;
@@ -1672,6 +1673,17 @@ void brw_CMP(struct brw_compile *p,
p->current->header.predicate_control = BRW_PREDICATE_NORMAL;
p->flag_value = 0xff;
}
+
+ /* Item WaCMPInstNullDstForcesThreadSwitch in the Haswell Bspec workarounds
+ * page says:
+ * "Any CMP instruction with a null destination must use a {switch}."
+ */
+ if (intel->is_haswell) {
+ if (dest.file == BRW_ARCHITECTURE_REGISTER_FILE &&
+ dest.nr == BRW_ARF_NULL) {
+ insn->header.thread_control = BRW_THREAD_SWITCH;
+ }
+ }
}
/* Issue 'wait' instruction for n1, host could program MMIO