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authorAnuj Phogat <[email protected]>2018-08-27 16:16:58 -0700
committerAnuj Phogat <[email protected]>2018-09-21 14:40:04 -0700
commit5eb173304bd1cebdde0617bcc42cd4dca0b8c880 (patch)
tree9b14cd353d164d806db7b26db73377ec450accf4
parentafb7c6b301ea4275d64498a0b62a908777cb9b24 (diff)
anv/icl: Set Enabled Texel Offset Precision Fix bit
h/w specification requires this bit to be always set. Suggested-by: Kenneth Graunke <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
-rw-r--r--src/intel/genxml/gen11.xml5
-rw-r--r--src/intel/vulkan/genX_state.c14
2 files changed, 19 insertions, 0 deletions
diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
index 1b3befbbfc9..c69d7dc89c2 100644
--- a/src/intel/genxml/gen11.xml
+++ b/src/intel/genxml/gen11.xml
@@ -3640,4 +3640,9 @@
<field name="Headerless Message for Pre-emptable Contexts Mask" start="21" end="21" type="bool"/>
</register>
+ <register name="HALF_SLICE_CHICKEN7" length="1" num="0x0e194">
+ <field name="Enabled Texel Offset Precision Fix" start="1" end="1" type="bool"/>
+ <field name="Enabled Texel Offset Precision Fix Mask" start="17" end="17" type="bool"/>
+ </register>
+
</genxml>
diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
index 4a175b9234d..aa5bce5a801 100644
--- a/src/intel/vulkan/genX_state.c
+++ b/src/intel/vulkan/genX_state.c
@@ -172,6 +172,20 @@ genX(init_device_state)(struct anv_device *device)
lri.RegisterOffset = GENX(SAMPLER_MODE_num);
lri.DataDWord = sampler_mode;
}
+
+ /* Bit 1 "Enabled Texel Offset Precision Fix" must be set in
+ * HALF_SLICE_CHICKEN7 register.
+ */
+ uint32_t half_slice_chicken7;
+ anv_pack_struct(&half_slice_chicken7, GENX(HALF_SLICE_CHICKEN7),
+ .EnabledTexelOffsetPrecisionFix = true,
+ .EnabledTexelOffsetPrecisionFixMask = true);
+
+ anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
+ lri.RegisterOffset = GENX(HALF_SLICE_CHICKEN7_num);
+ lri.DataDWord = half_slice_chicken7;
+ }
+
#endif
/* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so