diff options
| author | Nicolai Hähnle <[email protected]> | 2016-06-23 15:00:53 +0200 |
|---|---|---|
| committer | Nicolai Hähnle <[email protected]> | 2016-06-24 13:28:32 +0200 |
| commit | 2aa0485902cdb4cd02b72627a760b00e71bffecf (patch) | |
| tree | 171673b7ecbe9c6649fcb5edd794e5396e2bd7d1 | |
| parent | 82ab3f27ffed2f0f8e324a384dc4eab7f9f996be (diff) | |
radeonsi: use DRAW_(INDEX_)INDIRECT_MULTI on Polaris
The non-MULTI variants will be removed in Polaris firmware.
Cc: 12.0 <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_draw.c | 46 |
1 files changed, 36 insertions, 10 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 641becf7bc8..52737189fae 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -596,11 +596,24 @@ static void si_emit_draw_packets(struct si_context *sctx, radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0)); radeon_emit(cs, index_max_size); - radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_INDIRECT, 3, render_cond_bit)); - radeon_emit(cs, info->indirect_offset); - radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2); - radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2); - radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA); + if (sctx->b.family < CHIP_POLARIS10) { + radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_INDIRECT, 3, render_cond_bit)); + radeon_emit(cs, info->indirect_offset); + radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2); + radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2); + radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA); + } else { + radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_INDIRECT_MULTI, 8, render_cond_bit)); + radeon_emit(cs, info->indirect_offset); + radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2); + radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2); + radeon_emit(cs, 0); /* draw_index */ + radeon_emit(cs, 1); /* count */ + radeon_emit(cs, 0); /* count_addr -- disabled */ + radeon_emit(cs, 0); + radeon_emit(cs, 16); /* stride */ + radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA); + } } else { index_va += info->start * ib->index_size; @@ -623,11 +636,24 @@ static void si_emit_draw_packets(struct si_context *sctx, radeon_emit(cs, indirect_va); radeon_emit(cs, indirect_va >> 32); - radeon_emit(cs, PKT3(PKT3_DRAW_INDIRECT, 3, render_cond_bit)); - radeon_emit(cs, info->indirect_offset); - radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2); - radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2); - radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX); + if (sctx->b.family < CHIP_POLARIS10) { + radeon_emit(cs, PKT3(PKT3_DRAW_INDIRECT, 3, render_cond_bit)); + radeon_emit(cs, info->indirect_offset); + radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2); + radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2); + radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX); + } else { + radeon_emit(cs, PKT3(PKT3_DRAW_INDIRECT_MULTI, 8, render_cond_bit)); + radeon_emit(cs, info->indirect_offset); + radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2); + radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2); + radeon_emit(cs, 0); /* draw_index */ + radeon_emit(cs, 1); /* count */ + radeon_emit(cs, 0); /* count_addr -- disabled */ + radeon_emit(cs, 0); + radeon_emit(cs, 16); /* stride */ + radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX); + } } else { radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit)); radeon_emit(cs, info->count); |