diff options
| author | Rob Clark <[email protected]> | 2019-10-25 13:56:30 -0700 |
|---|---|---|
| committer | Rob Clark <[email protected]> | 2019-11-09 02:49:15 +0000 |
| commit | f0f9ec6882fc749943d9a7147318b7b05d74bf4f (patch) | |
| tree | 955828a3a80705b16e8e6a1d7c257aad0d5c9047 | |
| parent | df229977c38c0dbebfe59e9270de4013381c0735 (diff) | |
freedreno/a3xx: fix SP_FS_MRT_REG.HALF_PRECISION
We should really be setting this based on the actual output register
type.
Signed-off-by: Rob Clark <[email protected]>
| -rw-r--r-- | src/gallium/drivers/freedreno/a3xx/fd3_program.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_program.c b/src/gallium/drivers/freedreno/a3xx/fd3_program.c index a9d4fd0784f..893518935c8 100644 --- a/src/gallium/drivers/freedreno/a3xx/fd3_program.c +++ b/src/gallium/drivers/freedreno/a3xx/fd3_program.c @@ -321,7 +321,7 @@ fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit, OUT_PKT0(ring, REG_A3XX_SP_FS_MRT_REG(0), 4); for (i = 0; i < 4; i++) { uint32_t mrt_reg = A3XX_SP_FS_MRT_REG_REGID(color_regid[i]) | - COND(fp->key.half_precision, A3XX_SP_FS_MRT_REG_HALF_PRECISION); + COND(color_regid[i] & HALF_REG_ID, A3XX_SP_FS_MRT_REG_HALF_PRECISION); if (i < nr) { enum pipe_format fmt = pipe_surface_format(bufs[i]); |