diff options
| author | Jason Ekstrand <[email protected]> | 2019-09-01 22:12:07 -0500 |
|---|---|---|
| committer | Jason Ekstrand <[email protected]> | 2019-09-06 03:58:09 +0000 |
| commit | d15fe8ca8262d502435c4f83985ac414f950bc5f (patch) | |
| tree | 06893693485af114474d618f898409fbaf01e332 | |
| parent | 47e974354715702a75ad2f1ee803b72cbd8cc9f1 (diff) | |
Revert "intel/fs: Move the scalar-region conversion to the generator."
This reverts commit c0504569eac5e5c305e9f0c240e248aca9d8891f. Now that
we're doing interpolation lowering in NIR, we can continue to stride the
FS input registers directly in the brw_fs_nir code like we did before.
This fixes SIMD32 fragment shaders which broke because lower_simd_width
depended on the 0 stride to split PLN instructions correctly.
Reviewed-by: Francisco Jerez <[email protected]>
| -rw-r--r-- | src/intel/compiler/brw_fs.cpp | 2 | ||||
| -rw-r--r-- | src/intel/compiler/brw_fs_generator.cpp | 2 | ||||
| -rw-r--r-- | src/intel/compiler/brw_fs_nir.cpp | 4 | ||||
| -rw-r--r-- | src/intel/compiler/brw_fs_visitor.cpp | 2 |
4 files changed, 5 insertions, 5 deletions
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 381d10bfccd..f614fa85884 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -1192,7 +1192,7 @@ fs_visitor::emit_fragcoord_interpolation(fs_reg wpos) } else { bld.emit(FS_OPCODE_LINTERP, wpos, this->delta_xy[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL], - interp_reg(VARYING_SLOT_POS, 2)); + component(interp_reg(VARYING_SLOT_POS, 2), 0)); } wpos = offset(wpos, bld, 1); diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index 885e799ae76..b6e6925ac9e 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -795,7 +795,7 @@ fs_generator::generate_linterp(fs_inst *inst, */ struct brw_reg delta_x = src[0]; struct brw_reg delta_y = offset(src[0], inst->exec_size / 8); - struct brw_reg interp = stride(src[1], 0, 1, 0); + struct brw_reg interp = src[1]; brw_inst *i[2]; /* nir_lower_interpolation() will do the lowering to MAD instructions for diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index f003abc2014..4e2881756ea 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -3632,8 +3632,8 @@ fs_visitor::nir_emit_fs_intrinsic(const fs_builder &bld, for (unsigned int i = 0; i < instr->num_components; i++) { fs_reg interp = - interp_reg(nir_intrinsic_base(instr), - nir_intrinsic_component(instr) + i); + component(interp_reg(nir_intrinsic_base(instr), + nir_intrinsic_component(instr) + i), 0); interp.type = BRW_REGISTER_TYPE_F; dest.type = BRW_REGISTER_TYPE_F; diff --git a/src/intel/compiler/brw_fs_visitor.cpp b/src/intel/compiler/brw_fs_visitor.cpp index e8ff5568330..49eb9c00f1b 100644 --- a/src/intel/compiler/brw_fs_visitor.cpp +++ b/src/intel/compiler/brw_fs_visitor.cpp @@ -194,7 +194,7 @@ fs_visitor::emit_interpolation_setup_gen4() */ this->wpos_w = vgrf(glsl_type::float_type); abld.emit(FS_OPCODE_LINTERP, wpos_w, delta_xy, - interp_reg(VARYING_SLOT_POS, 3)); + component(interp_reg(VARYING_SLOT_POS, 3), 0)); /* Compute the pixel 1/W value from wpos.w. */ this->pixel_w = vgrf(glsl_type::float_type); abld.emit(SHADER_OPCODE_RCP, this->pixel_w, wpos_w); |