diff options
| author | Rhys Perry <[email protected]> | 2019-11-27 16:49:53 +0000 |
|---|---|---|
| committer | Rhys Perry <[email protected]> | 2019-12-02 10:48:27 +0000 |
| commit | a814f3d8a7d2e87ed357cd600408012f13c6a90d (patch) | |
| tree | 39807d020a7cc2df0c55e4ab2377830b58b43f0c | |
| parent | e61a826f39628d87a5ce534d687133ab768c1917 (diff) | |
ac/llvm: improve sync scope for global atomics
Stronger ordering is implemented in SPIRV->NIR with barriers.
Signed-off-by: Rhys Perry <[email protected]>
Reviewed-by: Samuel Pitoiset <[email protected]>
| -rw-r--r-- | src/amd/llvm/ac_nir_to_llvm.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c index ddf9f09fe0c..830866bc5cb 100644 --- a/src/amd/llvm/ac_nir_to_llvm.c +++ b/src/amd/llvm/ac_nir_to_llvm.c @@ -3024,6 +3024,9 @@ static LLVMValueRef visit_var_atomic(struct ac_nir_context *ctx, nir_deref_instr *deref = nir_instr_as_deref(instr->src[0].ssa->parent_instr); if (deref->mode == nir_var_mem_global) { + /* use "singlethread" sync scope to implement relaxed ordering */ + sync_scope = LLVM_VERSION_MAJOR >= 9 ? "singlethread-one-as" : "singlethread"; + LLVMTypeRef ptr_type = LLVMPointerType(LLVMTypeOf(src), LLVMGetPointerAddressSpace(LLVMTypeOf(ptr))); ptr = LLVMBuildBitCast(ctx->ac.builder, ptr, ptr_type , ""); } |