diff options
| author | Dave Airlie <[email protected]> | 2011-06-02 14:42:11 +1000 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2011-06-02 14:42:11 +1000 |
| commit | 991dbd71fdcc95e42bc56097d2fef3a7df0e8eaa (patch) | |
| tree | 2344ad8473f357d9ac1054f30a39cea86722fb74 | |
| parent | c1159eea54b28096652289ee8d06472566d9a4e5 (diff) | |
r600g: migrate macros from r600_priv.h to r600.h
this is just an precursor change for some later patches.
Signed-off-by: Dave Airlie <[email protected]>
| -rw-r--r-- | src/gallium/drivers/r600/r600.h | 11 | ||||
| -rw-r--r-- | src/gallium/winsys/r600/drm/r600_priv.h | 10 |
2 files changed, 11 insertions, 10 deletions
diff --git a/src/gallium/drivers/r600/r600.h b/src/gallium/drivers/r600/r600.h index b90de7c65d6..97bef42db05 100644 --- a/src/gallium/drivers/r600/r600.h +++ b/src/gallium/drivers/r600/r600.h @@ -145,6 +145,17 @@ static INLINE unsigned r600_bo_offset(struct r600_bo *bo) #define R600_BLOCK_MAX_BO 32 #define R600_BLOCK_MAX_REG 128 +/* each range covers 9 bits of dword space = 512 dwords = 2k bytes */ +/* there is a block entry for each register so 512 blocks */ +/* we have no registers to read/write below 0x8000 (0x2000 in dw space) */ +/* we use some fake offsets at 0x40000 to do evergreen sampler borders so take 0x42000 as a max bound*/ +#define RANGE_OFFSET_START 0x8000 +#define HASH_SHIFT 9 +#define NUM_RANGES (0x42000 - RANGE_OFFSET_START) / (4 << HASH_SHIFT) /* 128 << 9 = 64k */ + +#define CTX_RANGE_ID(offset) ((((offset - RANGE_OFFSET_START) >> 2) >> HASH_SHIFT) & 255) +#define CTX_BLOCK_ID(offset) (((offset - RANGE_OFFSET_START) >> 2) & ((1 << HASH_SHIFT) - 1)) + struct r600_pipe_reg { u32 offset; u32 mask; diff --git a/src/gallium/winsys/r600/drm/r600_priv.h b/src/gallium/winsys/r600/drm/r600_priv.h index 9093e332132..9be5c358f85 100644 --- a/src/gallium/winsys/r600/drm/r600_priv.h +++ b/src/gallium/winsys/r600/drm/r600_priv.h @@ -189,16 +189,6 @@ struct r600_bo *r600_bomgr_bo_create(struct r600_bomgr *mgr, * helpers */ -/* each range covers 9 bits of dword space = 512 dwords = 2k bytes */ -/* there is a block entry for each register so 512 blocks */ -/* we have no registers to read/write below 0x8000 (0x2000 in dw space) */ -/* we use some fake offsets at 0x40000 to do evergreen sampler borders so take 0x42000 as a max bound*/ -#define RANGE_OFFSET_START 0x8000 -#define HASH_SHIFT 9 -#define NUM_RANGES (0x42000 - RANGE_OFFSET_START) / (4 << HASH_SHIFT) /* 128 << 9 = 64k */ - -#define CTX_RANGE_ID(offset) ((((offset - RANGE_OFFSET_START) >> 2) >> HASH_SHIFT) & 255) -#define CTX_BLOCK_ID(offset) (((offset - RANGE_OFFSET_START) >> 2) & ((1 << HASH_SHIFT) - 1)) /* * radeon_bo.c |