diff options
| author | Erico Nunes <[email protected]> | 2019-07-22 00:55:24 +0200 |
|---|---|---|
| committer | Erico Nunes <[email protected]> | 2019-07-23 08:24:19 +0000 |
| commit | 9254059dd859d6bb8820525910ec028098e788e8 (patch) | |
| tree | 94e19b9d62a270675fd5e9ef4d340ee1de8614b2 | |
| parent | 9343c93e34b559d29f62209ed832f9f11773515a (diff) | |
lima/ppir: fix alignment on regalloc spilling loads
The spilling code spills entire vec4 registers regardless of the
components used by the spilled uses.
The inserted stores code force the 4 components, but these loads were
using a variable number of components, causing bugs on loading the
spilled registers.
Signed-off-by: Erico Nunes <[email protected]>
Reviewed-by: Qiang Yu <[email protected]>
| -rw-r--r-- | src/gallium/drivers/lima/ir/pp/regalloc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gallium/drivers/lima/ir/pp/regalloc.c b/src/gallium/drivers/lima/ir/pp/regalloc.c index 62401150e3e..3bd8569cf15 100644 --- a/src/gallium/drivers/lima/ir/pp/regalloc.c +++ b/src/gallium/drivers/lima/ir/pp/regalloc.c @@ -410,7 +410,7 @@ static ppir_alu_node* ppir_update_spilled_src(ppir_compiler *comp, ppir_load_node *load = ppir_node_to_load(load_node); load->index = -comp->prog->stack_size; /* index sizes are negative */ - load->num_components = src->reg->num_components; + load->num_components = 4; ppir_dest *ld_dest = &load->dest; ld_dest->type = ppir_target_pipeline; |