diff options
| author | Matt Turner <[email protected]> | 2018-12-10 11:48:54 -0800 |
|---|---|---|
| committer | Matt Turner <[email protected]> | 2019-01-09 16:42:41 -0800 |
| commit | 622d4291287b8dfad612b92945abd39e767a7b15 (patch) | |
| tree | 64020f518f234e1daa46115968448a6678102570 | |
| parent | 7e4e9da90d8b4a000357efa5c0e0027fd00c28b9 (diff) | |
intel/compiler: Expand size of the 'nr' field
Shaders containing software implementations of double-precision
operations can be very large such that we have more the 2^16 virtual
registers during optimization.
Move the 'nr' field to the union containing the immediate storage and
expand it to 32-bits.
Reviewed-by: Kenneth Graunke <[email protected]>
| -rw-r--r-- | src/intel/compiler/brw_reg.h | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/src/intel/compiler/brw_reg.h b/src/intel/compiler/brw_reg.h index 46d66198a1d..4543d841c66 100644 --- a/src/intel/compiler/brw_reg.h +++ b/src/intel/compiler/brw_reg.h @@ -221,15 +221,15 @@ struct brw_reg { unsigned negate:1; /* source only */ unsigned abs:1; /* source only */ unsigned address_mode:1; /* relative addressing, hopefully! */ - unsigned pad0:1; + unsigned pad0:17; unsigned subnr:5; /* :1 in align16 */ - unsigned nr:16; }; uint32_t bits; }; union { struct { + unsigned nr; unsigned swizzle:8; /* src only, align16 only */ unsigned writemask:4; /* dest only, align16 only */ int indirect_offset:10; /* relative addressing offset */ @@ -251,8 +251,7 @@ struct brw_reg { static inline bool brw_regs_equal(const struct brw_reg *a, const struct brw_reg *b) { - const bool df = a->type == BRW_REGISTER_TYPE_DF && a->file == IMM; - return a->bits == b->bits && (df ? a->u64 == b->u64 : a->ud == b->ud); + return a->bits == b->bits && a->u64 == b->u64; } static inline bool |