diff options
| author | Marek Olšák <[email protected]> | 2019-07-02 23:35:05 -0400 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2019-07-09 17:24:16 -0400 |
| commit | 4985c3ee22e291aa57dee66758f874ee95c0426c (patch) | |
| tree | b751c70fbef3134884e6654050d1abce2e50928f | |
| parent | 329406ec9c0aa8105c5e36281d68b5726c4aab49 (diff) | |
radeonsi/gfx10: set HS/GS/CS.WGP_MODE
Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Acked-by: Dave Airlie <[email protected]>
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_compute.c | 1 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_shaders.c | 3 |
2 files changed, 4 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c index f4fabca8635..6c3509b5226 100644 --- a/src/gallium/drivers/radeonsi/si_compute.c +++ b/src/gallium/drivers/radeonsi/si_compute.c @@ -191,6 +191,7 @@ static void si_create_compute_state_async(void *job, int thread_index) S_00B848_VGPRS((shader->config.num_vgprs - 1) / 4) | S_00B848_DX10_CLAMP(1) | S_00B848_MEM_ORDERED(sscreen->info.chip_class >= GFX10) | + S_00B848_WGP_MODE(sscreen->info.chip_class >= GFX10) | S_00B848_FLOAT_MODE(shader->config.float_mode); if (program->screen->info.chip_class < GFX10) { diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c index 5a3d534d475..14a3c3e0363 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.c +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c @@ -558,6 +558,7 @@ static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader) S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) : 0) | S_00B428_DX10_CLAMP(1) | S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) | + S_00B428_WGP_MODE(sscreen->info.chip_class >= GFX10) | S_00B428_FLOAT_MODE(shader->config.float_mode) | S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt)); @@ -898,6 +899,7 @@ static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader) S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) | S_00B228_DX10_CLAMP(1) | S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) | + S_00B228_WGP_MODE(sscreen->info.chip_class >= GFX10) | S_00B228_FLOAT_MODE(shader->config.float_mode) | S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt); uint32_t rsrc2 = @@ -1158,6 +1160,7 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader S_00B228_FLOAT_MODE(shader->config.float_mode) | S_00B228_DX10_CLAMP(1) | S_00B228_MEM_ORDERED(1) | + S_00B228_WGP_MODE(1) | S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt)); si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) | |