diff options
| author | Marek Olšák <[email protected]> | 2018-02-02 21:04:57 +0100 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2018-02-24 23:08:28 +0100 |
| commit | 41895c26d325dcc2b4ed464731d1c56afdf3bd6b (patch) | |
| tree | 3b55290461aeb0cbe3dc12fb495205e26232b040 | |
| parent | f0b39779a09de67d3576ae864bffee903523c69e (diff) | |
radeonsi: move TCS_OUT_LAYOUT.PatchVerticesIn to lower bits
For a later patch.
Reviewed-by: Nicolai Hähnle <[email protected]>
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_shader.c | 2 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_shader_internal.h | 2 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_draw.c | 7 |
3 files changed, 6 insertions, 5 deletions
diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index 6f8fee6c28e..efdf80b961e 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -2014,7 +2014,7 @@ static LLVMValueRef si_load_patch_vertices_in(struct ac_shader_abi *abi) { struct si_shader_context *ctx = si_shader_context_from_abi(abi); if (ctx->type == PIPE_SHADER_TESS_CTRL) - return unpack_param(ctx, ctx->param_tcs_out_lds_layout, 26, 6); + return unpack_param(ctx, ctx->param_tcs_out_lds_layout, 13, 6); else if (ctx->type == PIPE_SHADER_TESS_EVAL) return get_num_tcs_out_vertices(ctx); else diff --git a/src/gallium/drivers/radeonsi/si_shader_internal.h b/src/gallium/drivers/radeonsi/si_shader_internal.h index 42a1b9f107c..40947ffc079 100644 --- a/src/gallium/drivers/radeonsi/si_shader_internal.h +++ b/src/gallium/drivers/radeonsi/si_shader_internal.h @@ -162,7 +162,7 @@ struct si_shader_context { /* Layout of TCS outputs / TES inputs: * [0:12] = stride between output patches in DW, num_outputs * num_vertices * 4 * max = 32*32*4 + 32*4 - * [26:31] = gl_PatchVerticesIn, max = 32 + * [13:18] = gl_PatchVerticesIn, max = 32 */ int param_tcs_out_lds_layout; int param_tcs_offchip_addr_base64k; diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 06ef84d20da..b245a383987 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -233,7 +233,8 @@ static void si_emit_derived_tess_state(struct si_context *sctx, tcs_in_layout = S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size / 4) | S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size / 4); - tcs_out_layout = output_patch_size / 4; + tcs_out_layout = (output_patch_size / 4) | + (num_tcs_input_cp << 13); tcs_out_offsets = (output_patch0_offset / 16) | ((perpatch_output_offset / 16) << 16); offchip_layout = *num_patches | @@ -268,7 +269,7 @@ static void si_emit_derived_tess_state(struct si_context *sctx, GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4, 3); radeon_emit(cs, offchip_layout); radeon_emit(cs, tcs_out_offsets); - radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26)); + radeon_emit(cs, tcs_out_layout); } else { unsigned ls_rsrc2 = ls_current->config.rsrc2; @@ -288,7 +289,7 @@ static void si_emit_derived_tess_state(struct si_context *sctx, R_00B430_SPI_SHADER_USER_DATA_HS_0 + GFX6_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4); radeon_emit(cs, offchip_layout); radeon_emit(cs, tcs_out_offsets); - radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26)); + radeon_emit(cs, tcs_out_layout); radeon_emit(cs, tcs_in_layout); } |