i965/vec4: Don't trim writemasks of texture instructions.

It was my understanding that the writemask works in SIMD4x2 mode for
texturing instructions and doesn't require a message header. Some bit of
this logic must be wrong, so disable it until it's understood.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76617
Reviewed-by: Kenneth Graunke <[email protected]>

1 files changed, 4 insertions, 2 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 4ae60208f2c..32a38920dd2 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -351,8 +351,10 @@ try_eliminate_instruction(vec4_instruction *inst, int new_writemask)
       case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
          break;
       default:
-         inst->dst.writemask = new_writemask;
-         return true;
+         if (!inst->is_tex()) {
+            inst->dst.writemask = new_writemask;
+            return true;
+         }
       }
    }