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authorEric Anholt <[email protected]>2011-06-20 08:52:03 -0700
committerEric Anholt <[email protected]>2011-06-23 13:41:42 -0700
commitbabe1fc004b56202b2bd54d9689f5208dc4fd607 (patch)
tree9c85fab89492e08346223a2e84c09d788c755683
parent935e7e41266186c454e08c80aff40c34084d83c6 (diff)
i965/gen6: Add a couple more packets to the nonpipelined workaround list.
All the packets chosen before came from grepping the pdf for nonpipelined, and these two came from grepping for non.pipelined. We could stand a review by looking at all packets emitted and identifying what kind they are.
-rw-r--r--src/mesa/drivers/dri/i965/brw_misc_state.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index c23569679e4..ea2e6013de6 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -449,6 +449,9 @@ static void upload_polygon_stipple(struct brw_context *brw)
if (!ctx->Polygon.StippleFlag)
return;
+ if (intel->gen == 6)
+ intel_emit_post_sync_nonzero_flush(intel);
+
BEGIN_BATCH(33);
OUT_BATCH(_3DSTATE_POLY_STIPPLE_PATTERN << 16 | (33 - 2));
@@ -492,6 +495,9 @@ static void upload_polygon_stipple_offset(struct brw_context *brw)
if (!ctx->Polygon.StippleFlag)
return;
+ if (intel->gen == 6)
+ intel_emit_post_sync_nonzero_flush(intel);
+
BEGIN_BATCH(2);
OUT_BATCH(_3DSTATE_POLY_STIPPLE_OFFSET << 16 | (2-2));