diff options
| author | Dave Airlie <[email protected]> | 2017-03-30 08:13:48 +0100 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2017-04-01 07:16:04 +1000 |
| commit | 5b40eab00ad079bcd173234c879d3a8ebf7fe9ec (patch) | |
| tree | 59bc2a0d6c539c143fee6fddb770800d44b5b6ca | |
| parent | 3a633cc2cbd0a527ac97cfe60a9d66df18b7de64 (diff) | |
radv: add tess ctrl stage barrier workaround for SI.
This just ports the workaround from radeonsi.
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
| -rw-r--r-- | src/amd/common/ac_nir_to_llvm.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index cb7469168cd..8f56fbf1eb0 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c @@ -2917,9 +2917,17 @@ static void emit_waitcnt(struct nir_to_llvm_context *ctx, static void emit_barrier(struct nir_to_llvm_context *ctx) { - // TODO tess + /* SI only (thanks to a hw bug workaround): + * The real barrier instruction isn’t needed, because an entire patch + * always fits into a single wave. + */ + if (ctx->options->chip_class == SI && + ctx->stage == MESA_SHADER_TESS_CTRL) { + emit_waitcnt(ctx, LGKM_CNT & VM_CNT); + return; + } ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier", - ctx->voidt, NULL, 0, 0); + ctx->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT); } static void emit_discard_if(struct nir_to_llvm_context *ctx, |