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authorKenneth Graunke <[email protected]>2013-10-24 00:45:56 -0700
committerKenneth Graunke <[email protected]>2013-10-28 11:29:31 -0700
commit10a918e52c37715744f7980b2bc9da69575514da (patch)
tree075280bd72d67390fd4e9533759e3c922c9b89b2
parent3aef1fefb4dc2a66101725f2fdc3f2bb0eb926c2 (diff)
i965: Also guard 3DSTATE_DRAWING_RECTANGLE with a flush in blorp.
Non-pipelined commands need this flush. Signed-off-by: Kenneth Graunke <[email protected]> Tested-by: Xinkai Chen <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Cc: "9.2" <[email protected]>
-rw-r--r--src/mesa/drivers/dri/i965/gen6_blorp.cpp3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index da523e5bffe..ce215c2949e 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -957,6 +957,9 @@ void
gen6_blorp_emit_drawing_rectangle(struct brw_context *brw,
const brw_blorp_params *params)
{
+ if (brw->gen == 6)
+ intel_emit_post_sync_nonzero_flush(brw);
+
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2));
OUT_BATCH(0);