diff options
author | Eric Anholt <[email protected]> | 2010-03-10 10:38:20 -0800 |
---|---|---|
committer | Eric Anholt <[email protected]> | 2010-03-10 10:44:08 -0800 |
commit | f6d210c284751ac50a8d6358de7e75a1ff1e4ac7 (patch) | |
tree | c67a4e741304c72b9ab5bc5e0fdfbb8eb55a31d5 | |
parent | c8ef7a09664d29dac682b953eb66efaebbdd6fd7 (diff) |
i965: Fix the response len of masked sampler messages for 8-wide dispatch.
The bad response length would hang the GPU with a masked sample in a
shader using control flow. For 8-wide, the response length is always
4, and masked slots are just not written to. brw_wm_glsl.c already
allocates registers in the right locations.
Fixes piglit glsl-fs-bug25902 (fd.o bug #25902).
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_eu_emit.c | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index f69d5296137..40c1b719984 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -1290,7 +1290,11 @@ void brw_SAMPLE(struct brw_compile *p, GLuint simd_mode) { GLboolean need_stall = 0; - + GLboolean dispatch_16 = GL_FALSE; + + if (p->current->header.execution_size == BRW_EXECUTE_16) + dispatch_16 = GL_TRUE; + if (writemask == 0) { /*printf("%s: zero writemask??\n", __FUNCTION__); */ return; @@ -1343,7 +1347,13 @@ void brw_SAMPLE(struct brw_compile *p, src0 = retype(brw_null_reg(), BRW_REGISTER_TYPE_UW); dest = offset(dest, dst_offset); - response_length = len * 2; + + /* For 16-wide dispatch, masked channels are skipped in the + * response. For 8-wide, masked channels still take up slots, + * and are just not written to. + */ + if (dispatch_16) + response_length = len * 2; } } |