diff options
| author | Jason Ekstrand <[email protected]> | 2016-06-04 20:48:55 -0700 |
|---|---|---|
| committer | Jason Ekstrand <[email protected]> | 2016-06-22 12:26:43 -0700 |
| commit | d050ffbce950f8ececd12200145eb209819a421e (patch) | |
| tree | 6dedd3475122a135006a346aa36b557c71bca5c2 | |
| parent | 87f0ffa646e97def0f81ba2ad12eab2702dfd7b1 (diff) | |
isl/state: Don't force-disable L2 bypass for everything
We already set the bit in the few cases where it's required by the docs so
there's no need to set it all the time. This has no noticable perf impact
for Dota 2 on Vulkan with the time demo I have.
Reviewed-by: Chad Versace <[email protected]>
Cc: "12.0" <[email protected]>
| -rw-r--r-- | src/intel/isl/isl_surface_state.c | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index f36c0199ada..89fd69d877f 100644 --- a/src/intel/isl/isl_surface_state.c +++ b/src/intel/isl/isl_surface_state.c @@ -311,10 +311,6 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, #endif #if GEN_GEN >= 8 - s.SamplerL2BypassModeDisable = true; -#endif - -#if GEN_GEN >= 8 s.RenderCacheReadWriteMode = WriteOnlyCache; #else s.RenderCacheReadWriteMode = 0; @@ -431,7 +427,6 @@ isl_genX(buffer_fill_state_s)(void *state, #endif #if (GEN_GEN >= 8) - .SamplerL2BypassModeDisable = true, .RenderCacheReadWriteMode = WriteOnlyCache, #else .RenderCacheReadWriteMode = 0, |