diff options
| author | Marek Olšák <[email protected]> | 2016-10-15 14:21:59 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2017-03-30 14:44:33 +0200 |
| commit | 5f4659260ec4bc49d951aa93da2945c1fbde9e2e (patch) | |
| tree | 7437213bf155f6730fad2d63d6df94f3b542dab5 | |
| parent | d214b95e9a113733865546f3388a38bdee69a95f (diff) | |
radeonsi/gfx9: ELEMENT_SIZE change
Reviewed-by: Nicolai Hähnle <[email protected]>
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_compute.c | 16 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_descriptors.c | 6 |
2 files changed, 15 insertions, 7 deletions
diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c index 913a2ddbfe6..33ebe2e7d97 100644 --- a/src/gallium/drivers/radeonsi/si_compute.c +++ b/src/gallium/drivers/radeonsi/si_compute.c @@ -468,16 +468,20 @@ static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx, /* Disable address clamping */ uint32_t scratch_dword2 = 0xffffffff; uint32_t scratch_dword3 = - S_008F0C_ELEMENT_SIZE(max_private_element_size) | S_008F0C_INDEX_STRIDE(3) | S_008F0C_ADD_TID_ENABLE(1); + if (sctx->b.chip_class >= GFX9) { + assert(max_private_element_size == 1); /* always 4 bytes on GFX9 */ + } else { + scratch_dword3 |= S_008F0C_ELEMENT_SIZE(max_private_element_size); - if (sctx->screen->b.chip_class < VI) { - /* BUF_DATA_FORMAT is ignored, but it cannot be - BUF_DATA_FORMAT_INVALID. */ - scratch_dword3 |= - S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8); + if (sctx->b.chip_class < VI) { + /* BUF_DATA_FORMAT is ignored, but it cannot be + * BUF_DATA_FORMAT_INVALID. */ + scratch_dword3 |= + S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8); + } } radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 + diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index c13bc942dc7..71b511c958d 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -1331,10 +1331,14 @@ void si_set_ring_buffer(struct pipe_context *ctx, uint slot, S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) | S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) | S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) | - S_008F0C_ELEMENT_SIZE(element_size) | S_008F0C_INDEX_STRIDE(index_stride) | S_008F0C_ADD_TID_ENABLE(add_tid); + if (sctx->b.chip_class >= GFX9) + assert(!swizzle || element_size == 1); /* always 4 bytes on GFX9 */ + else + desc[3] |= S_008F0C_ELEMENT_SIZE(element_size); + pipe_resource_reference(&buffers->buffers[slot], buffer); radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, (struct r600_resource*)buffer, |