diff options
| author | Ilia Mirkin <[email protected]> | 2015-09-10 23:58:17 -0400 |
|---|---|---|
| committer | Ilia Mirkin <[email protected]> | 2015-09-14 17:26:25 -0400 |
| commit | 5877a594d54fdd2b3aa329f4d35b3491a7ee8a33 (patch) | |
| tree | 3e74d4ae7104b2541dd854897c3fc17c5ffea70d | |
| parent | 64aee8fe9f28646ceb5b9b62db5766365d6da5c7 (diff) | |
nvc0/ir: start offset at texBindBase for txq, like regular texturing
Curiously this has no actual effect. I think it's because the first 8
textures are bound in multiple slots for some reason. However seems
prudent to use these the same way as regular texturing, esp in the case
where there are more than 8 textures bound.
Signed-off-by: Ilia Mirkin <[email protected]>
| -rw-r--r-- | src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp index b1f406585a9..b3fc73a2beb 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp @@ -962,11 +962,14 @@ NVC0LoweringPass::handleTXD(TexInstruction *txd) bool NVC0LoweringPass::handleTXQ(TexInstruction *txq) { + const int chipset = prog->getTarget()->getChipset(); + if (chipset >= NVISA_GK104_CHIPSET && txq->tex.rIndirectSrc < 0) + txq->tex.r += prog->driver->io.texBindBase / 4; + if (txq->tex.rIndirectSrc < 0) return true; Value *ticRel = txq->getIndirectR(); - const int chipset = prog->getTarget()->getChipset(); txq->setIndirectS(NULL); txq->tex.sIndirectSrc = -1; |