diff options
| author | Marek Olšák <[email protected]> | 2018-03-27 21:19:15 -0400 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2018-04-13 12:31:04 -0400 |
| commit | 29a09e1d380375bd3483d52ac5efdc8b47cc9851 (patch) | |
| tree | 8e55624858972143714c6be039a91b661dbc4cbe | |
| parent | 5fb31a1734b7f52846090b9cfadf5fac4822f500 (diff) | |
radeonsi: don't flush HTILE if there is no HTILE clear
Reviewed-by: Samuel Pitoiset <[email protected]>
Tested-by: Dieter Nützel <[email protected]>
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_clear.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c index f8136d2b2c4..4e05d9bf5b2 100644 --- a/src/gallium/drivers/radeonsi/si_clear.c +++ b/src/gallium/drivers/radeonsi/si_clear.c @@ -593,9 +593,9 @@ static void si_clear(struct pipe_context *ctx, unsigned buffers, * * This hack decreases back-to-back ClearDepth performance. */ - if (sctx->screen->clear_db_cache_before_clear) { + if ((sctx->db_depth_clear || sctx->db_stencil_clear) && + sctx->screen->clear_db_cache_before_clear) sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB; - } } si_blitter_begin(sctx, SI_CLEAR); |