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authorIago Toral Quiroga <[email protected]>2016-09-28 13:03:00 +0200
committerSamuel Iglesias Gonsálvez <[email protected]>2017-01-03 11:26:51 +0100
commit017c8df35b343de0bb23220d030089bf57fb28d4 (patch)
tree8fa64e7ac7c6cd86398b37a0e24cf663a085c2c3
parentb3a7d0ee9d5f792ab68fbe77da5e3ea85d4bc4c0 (diff)
i965/vec4: support multiple dispatch widths and groups in the IR builder.
Reviewed-by: Matt Turner <[email protected]>
-rw-r--r--src/mesa/drivers/dri/i965/brw_vec4_builder.h39
1 files changed, 37 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_builder.h b/src/mesa/drivers/dri/i965/brw_vec4_builder.h
index dab6e0377fe..8352542d498 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_builder.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4_builder.h
@@ -52,8 +52,9 @@ namespace brw {
/**
* Construct a vec4_builder that inserts instructions into \p shader.
*/
- vec4_builder(backend_shader *shader) :
+ vec4_builder(backend_shader *shader, unsigned dispatch_width = 8) :
shader(shader), block(NULL), cursor(NULL),
+ _dispatch_width(dispatch_width), _group(0),
force_writemask_all(false),
annotation()
{
@@ -67,6 +68,7 @@ namespace brw {
*/
vec4_builder(backend_shader *shader, bblock_t *block, instruction *inst) :
shader(shader), block(block), cursor(inst),
+ _dispatch_width(inst->exec_size), _group(inst->group),
force_writemask_all(inst->force_writemask_all)
{
annotation.str = inst->annotation;
@@ -99,6 +101,25 @@ namespace brw {
}
/**
+ * Construct a builder specifying the default SIMD width and group of
+ * channel enable signals, inheriting other code generation parameters
+ * from this.
+ *
+ * \p n gives the default SIMD width, \p i gives the slot group used for
+ * predication and control flow masking in multiples of \p n channels.
+ */
+ vec4_builder
+ group(unsigned n, unsigned i) const
+ {
+ assert(force_writemask_all ||
+ (n <= dispatch_width() && i < dispatch_width() / n));
+ vec4_builder bld = *this;
+ bld._dispatch_width = n;
+ bld._group += i * n;
+ return bld;
+ }
+
+ /**
* Construct a builder with per-channel control flow execution masking
* disabled if \p b is true. If control flow execution masking is
* already disabled this has no effect.
@@ -130,7 +151,16 @@ namespace brw {
unsigned
dispatch_width() const
{
- return 8;
+ return _dispatch_width;
+ }
+
+ /**
+ * Get the channel group in use.
+ */
+ unsigned
+ group() const
+ {
+ return _group;
}
/**
@@ -281,7 +311,10 @@ namespace brw {
instruction *
emit(instruction *inst) const
{
+ inst->exec_size = dispatch_width();
+ inst->group = group();
inst->force_writemask_all = force_writemask_all;
+ inst->size_written = inst->exec_size * type_sz(inst->dst.type);
inst->annotation = annotation.str;
inst->ir = annotation.ir;
@@ -587,6 +620,8 @@ namespace brw {
bblock_t *block;
exec_node *cursor;
+ unsigned _dispatch_width;
+ unsigned _group;
bool force_writemask_all;
/** Debug annotation info. */