diff options
author | Jose Fonseca <[email protected]> | 2015-10-23 11:40:25 +0100 |
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committer | Jose Fonseca <[email protected]> | 2015-10-23 20:25:19 +0100 |
commit | ea421e919ae6e72e1319fb205c42a6fb53ca2f82 (patch) | |
tree | 62ec43189e1c80c9cf5ed32135854f12283a2612 | |
parent | 70b06fb5d55d639fd74596a2ff6971cb57c030ca (diff) |
gallivm: Explicitly disable unsupported CPU features.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92214
CC: "10.6 11.0" <[email protected]>
Reviewed-by: Roland Scheidegger <[email protected]>
-rw-r--r-- | src/gallium/auxiliary/gallivm/lp_bld_misc.cpp | 72 |
1 files changed, 34 insertions, 38 deletions
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp index e70a75fc663..7bda1184ee9 100644 --- a/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp +++ b/src/gallium/auxiliary/gallivm/lp_bld_misc.cpp @@ -498,50 +498,46 @@ lp_build_create_jit_compiler_for_module(LLVMExecutionEngineRef *OutJIT, } llvm::SmallVector<std::string, 16> MAttrs; - if (util_cpu_caps.has_sse) { - MAttrs.push_back("+sse"); - } - if (util_cpu_caps.has_sse2) { - MAttrs.push_back("+sse2"); - } - if (util_cpu_caps.has_sse3) { - MAttrs.push_back("+sse3"); - } - if (util_cpu_caps.has_ssse3) { - MAttrs.push_back("+ssse3"); - } - if (util_cpu_caps.has_sse4_1) { + +#if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64) + /* + * We need to unset attributes because sometimes LLVM mistakenly assumes + * certain features are present given the processor name. + * + * https://bugs.freedesktop.org/show_bug.cgi?id=92214 + * http://llvm.org/PR25021 + * http://llvm.org/PR19429 + * http://llvm.org/PR16721 + */ + MAttrs.push_back(util_cpu_caps.has_sse ? "+sse" : "-sse" ); + MAttrs.push_back(util_cpu_caps.has_sse2 ? "+sse2" : "-sse2" ); + MAttrs.push_back(util_cpu_caps.has_sse3 ? "+sse3" : "-sse3" ); + MAttrs.push_back(util_cpu_caps.has_ssse3 ? "+ssse3" : "-ssse3" ); #if HAVE_LLVM >= 0x0304 - MAttrs.push_back("+sse4.1"); + MAttrs.push_back(util_cpu_caps.has_sse4_1 ? "+sse4.1" : "-sse4.1"); #else - MAttrs.push_back("+sse41"); + MAttrs.push_back(util_cpu_caps.has_sse4_1 ? "+sse41" : "-sse41" ); #endif - } - if (util_cpu_caps.has_sse4_2) { #if HAVE_LLVM >= 0x0304 - MAttrs.push_back("+sse4.2"); + MAttrs.push_back(util_cpu_caps.has_sse4_2 ? "+sse4.2" : "-sse4.2"); #else - MAttrs.push_back("+sse42"); + MAttrs.push_back(util_cpu_caps.has_sse4_2 ? "+sse42" : "-sse42" ); #endif - } - if (util_cpu_caps.has_avx) { - /* - * AVX feature is not automatically detected from CPUID by the X86 target - * yet, because the old (yet default) JIT engine is not capable of - * emitting the opcodes. On newer llvm versions it is and at least some - * versions (tested with 3.3) will emit avx opcodes without this anyway. - */ - MAttrs.push_back("+avx"); - if (util_cpu_caps.has_f16c) { - MAttrs.push_back("+f16c"); - } - if (util_cpu_caps.has_avx2) { - MAttrs.push_back("+avx2"); - } - } - if (util_cpu_caps.has_altivec) { - MAttrs.push_back("+altivec"); - } + /* + * AVX feature is not automatically detected from CPUID by the X86 target + * yet, because the old (yet default) JIT engine is not capable of + * emitting the opcodes. On newer llvm versions it is and at least some + * versions (tested with 3.3) will emit avx opcodes without this anyway. + */ + MAttrs.push_back(util_cpu_caps.has_avx ? "+avx" : "-avx"); + MAttrs.push_back(util_cpu_caps.has_f16c ? "+f16c" : "-f16c"); + MAttrs.push_back(util_cpu_caps.has_avx2 ? "+avx2" : "-avx2"); +#endif + +#if defined(PIPE_ARCH_PPC) + MAttrs.push_back(util_cpu_caps.has_altivec ? "+altivec" : "-altivec"); +#endif + builder.setMAttrs(MAttrs); #if HAVE_LLVM >= 0x0305 |