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authorDave Airlie <[email protected]>2017-02-28 16:26:55 +1000
committerDave Airlie <[email protected]>2017-03-01 08:02:24 +1000
commite66be3d3bb40160c7b7d57c596e4a25da168f1e6 (patch)
treebfce94f31d6c38b4643bb7e5bc171b8ca873fb27
parent8c838730d070cbf4da035593b374e3c5566cf944 (diff)
radv: fix txs for sampler buffers
I messed this up when I wrote it, this fixes: dEQP-VK.memory.pipeline_barrier.*uniform_texel_buffer.* Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.0" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
-rw-r--r--src/amd/common/ac_nir_to_llvm.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index db7194c3086..a3310e10a72 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -3625,7 +3625,7 @@ static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
}
if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
- result = get_buffer_size(ctx, res_ptr, false);
+ result = get_buffer_size(ctx, res_ptr, true);
goto write_result;
}