diff options
| author | Roland Scheidegger <[email protected]> | 2007-11-15 01:13:16 +0100 |
|---|---|---|
| committer | Roland Scheidegger <[email protected]> | 2007-11-15 01:13:16 +0100 |
| commit | 96ba38a450b77d56730fd293499cbeaa1f511507 (patch) | |
| tree | e68d2b72d3866ffcc37e203eb96671f6b1ddeca5 | |
| parent | dab7c810e99e8fd2a7c8ba5cdbdc2fb6502647b3 (diff) | |
fix bogus assumption if ddx has set up surface reg for z buffer
this is wrong since even if ddx has not set up a surface reg to cover the z
buffer we should pretend it has on those rv100 chips since they presumably do
not do z buffer tiling if not using hyperz, so we can use linear addressing
just the same. Doesn't seem to fix #13080, but it's wrong anyway and the bug
almost certainly broke newer non-tcl chips.
| -rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_screen.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index ceb947c09d2..c12eef20242 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -720,8 +720,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) screen->depthPitch = dri_priv->depthPitch; /* Check if ddx has set up a surface reg to cover depth buffer */ - screen->depthHasSurface = ((sPriv->ddx_version.major > 4) && - (screen->chip_flags & RADEON_CHIPSET_TCL)); + screen->depthHasSurface = (sPriv->ddx_version.major > 4); if ( dri_priv->textureSize == 0 ) { screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset; |