diff options
| author | Eric Anholt <[email protected]> | 2010-08-27 12:19:30 -0700 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2010-08-27 12:21:40 -0700 |
| commit | 40932c1752b0fa918d764e3367f5ab450033304a (patch) | |
| tree | 06a55dff608c01bd6ff26dc2fce5fa85795be4c9 | |
| parent | 166b3fa29d4b5af8d4e8c410ed71e4348b65bbd9 (diff) | |
i965: Fix the maximum grf counting in the new FS backend.
glsl-algebraic-rcp-rsq managed to use 33 registers, and we claimed to
only use 32, so the write to g32 would go stomping over the precious
g0 of some other thread.
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index f8b06226d79..673a31c1dd6 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -1357,7 +1357,7 @@ fs_visitor::assign_regs() last_grf = MAX2(last_grf, inst->src[1].hw_reg); } - this->grf_used = last_grf; + this->grf_used = last_grf + 1; } static struct brw_reg brw_reg_from_fs_reg(fs_reg *reg) |