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authorFrancisco Jerez <[email protected]>2016-06-30 19:41:49 -0700
committerFrancisco Jerez <[email protected]>2016-07-07 14:16:39 -0700
commita10879f48cedb1ef906becba0abad0af27482f34 (patch)
treec08bee6505d022e2a8f4457779a87d42f104643b
parent04f74d66293222d5e1905cfb930bfa083e30463c (diff)
i965: Emit SKL VF cache invalidation W/A from brw_emit_pipe_control_flush.
There were two places in the driver doing a pipe control VF cache flush, one of them was missing this workaround, move it down into brw_emit_pipe_control_flush to make sure we don't miss it again. Cc: "12.0 11.1 11.2" <[email protected]> Reviewed-by: Alejandro PiƱeiro <[email protected]>
-rw-r--r--src/mesa/drivers/dri/i965/brw_pipe_control.c19
1 files changed, 10 insertions, 9 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index 586355d8c22..14a8f7c7cdb 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -100,6 +100,16 @@ brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags)
if (brw->gen == 8)
gen8_add_cs_stall_workaround_bits(&flags);
+ if (brw->gen == 9 &&
+ (flags & PIPE_CONTROL_VF_CACHE_INVALIDATE)) {
+ /* Hardware workaround: SKL
+ *
+ * Emit Pipe Control with all bits set to zero before emitting
+ * a Pipe Control with VF Cache Invalidate set.
+ */
+ brw_emit_pipe_control_flush(brw, 0);
+ }
+
BEGIN_BATCH(6);
OUT_BATCH(_3DSTATE_PIPE_CONTROL | (6 - 2));
OUT_BATCH(flags);
@@ -322,15 +332,6 @@ brw_emit_mi_flush(struct brw_context *brw)
} else {
int flags = PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_RENDER_TARGET_FLUSH;
if (brw->gen >= 6) {
- if (brw->gen == 9) {
- /* Hardware workaround: SKL
- *
- * Emit Pipe Control with all bits set to zero before emitting
- * a Pipe Control with VF Cache Invalidate set.
- */
- brw_emit_pipe_control_flush(brw, 0);
- }
-
flags |= PIPE_CONTROL_INSTRUCTION_INVALIDATE |
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
PIPE_CONTROL_VF_CACHE_INVALIDATE |