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authorKenneth Graunke <[email protected]>2014-02-10 16:48:14 -0800
committerKenneth Graunke <[email protected]>2014-02-19 15:43:22 -0800
commit4af8c95783acb632befa40c5bfc7fc58b62873d0 (patch)
treead83e21f405157538f95e5869e7ef158dd221d8e
parent51145a24f7938a4d5575d8d9aa4f8afa369d836b (diff)
i965: Update physical width/height munging for 2x IMS MSAA.
I can't find any documentation to explain what ought to be done here, so I simply guessed based on the pattern I observed in the 4x/8x cases. It appears to work, but it could be totally wrong. I was able to find the Sandybridge PRM quote from the comments in the latest documentation: Shared Functions > 3D Sampler > Multisampled Surface Behavior. However, it only mentions 4x MSAA - not even 8x. After a substantial amount more digging, I was able to find a second page (incorrectly tagged) which confirmed the formulas in our code for 8x MSAA. However, that page didn't mention 2x MSAA at all. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
-rw-r--r--src/mesa/drivers/dri/i965/intel_mipmap_tree.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index ba59ecdc67b..5461562d458 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -313,6 +313,11 @@ intel_miptree_create_layout(struct brw_context *brw,
* sample 3 is in that bottom right 2x2 block.
*/
switch (num_samples) {
+ case 2:
+ assert(brw->gen >= 8);
+ width0 = ALIGN(width0, 2) * 2;
+ height0 = ALIGN(height0, 2);
+ break;
case 4:
width0 = ALIGN(width0, 2) * 2;
height0 = ALIGN(height0, 2) * 2;
@@ -322,7 +327,7 @@ intel_miptree_create_layout(struct brw_context *brw,
height0 = ALIGN(height0, 2) * 2;
break;
default:
- /* num_samples should already have been quantized to 0, 1, 4, or
+ /* num_samples should already have been quantized to 0, 1, 2, 4, or
* 8.
*/
assert(false);