diff options
| author | Nicolai Hähnle <[email protected]> | 2018-06-19 17:44:24 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2019-07-03 15:51:12 -0400 |
| commit | fd8758366bce3cf764ef47c2aa5ddf461875b4c9 (patch) | |
| tree | 07d8f13f3545772a6df93de47229066d43f50100 | |
| parent | 48810ad02d411aa612ac316f4773f0fbe224b655 (diff) | |
radeonsi/gfx10: set llvm_has_working_vgpr_indexing
Acked-by: Bas Nieuwenhuizen <[email protected]>
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_pipe.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 9ea08c8fb26..7eaa400849e 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -1140,10 +1140,9 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws, } /* While it would be nice not to have this flag, we are constrained - * by the reality that LLVM 5.0 doesn't have working VGPR indexing - * on GFX9. + * by the reality that LLVM 9.0 has buggy VGPR indexing on GFX9. */ - sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class <= GFX8; + sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class != GFX9; /* Some chips have RB+ registers, but don't support RB+. Those must * always disable it. |