diff options
| author | Nicolai Hähnle <[email protected]> | 2018-05-30 22:45:06 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2019-07-03 15:51:12 -0400 |
| commit | ccdf79291049c2fb1f87d199f8f110f23532e903 (patch) | |
| tree | 92944736a1116ea0981941cc7c7f98f74e2a8fd6 | |
| parent | 00707922d40dfc6b8f439ddea15157e30b6975fe (diff) | |
radeonsi/gfx10: set USER_DATA_ADDR offset for geometry shaders
Acked-by: Bas Nieuwenhuizen <[email protected]>
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_descriptors.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index a9bafb1112b..262f7e88c93 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -2752,7 +2752,10 @@ void si_init_all_descriptors(struct si_context *sctx) if (i == PIPE_SHADER_TESS_CTRL) { rel_dw_offset = (R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS - R_00B430_SPI_SHADER_USER_DATA_LS_0) / 4; - } else { /* PIPE_SHADER_GEOMETRY */ + } else if (sctx->chip_class >= GFX10) { /* PIPE_SHADER_GEOMETRY */ + rel_dw_offset = (R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS - + R_00B230_SPI_SHADER_USER_DATA_GS_0) / 4; + } else { rel_dw_offset = (R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS - R_00B330_SPI_SHADER_USER_DATA_ES_0) / 4; } @@ -2770,7 +2773,10 @@ void si_init_all_descriptors(struct si_context *sctx) if (i == PIPE_SHADER_TESS_CTRL) { rel_dw_offset = (R_00B40C_SPI_SHADER_USER_DATA_ADDR_HI_HS - R_00B430_SPI_SHADER_USER_DATA_LS_0) / 4; - } else { /* PIPE_SHADER_GEOMETRY */ + } else if (sctx->chip_class >= GFX10) { /* PIPE_SHADER_GEOMETRY */ + rel_dw_offset = (R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS - + R_00B230_SPI_SHADER_USER_DATA_GS_0) / 4; + } else { rel_dw_offset = (R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS - R_00B330_SPI_SHADER_USER_DATA_ES_0) / 4; } |