i965: When encountering an unknown opcode in new FS backend, print its name.

3 files changed, 23 insertions, 14 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 3728a7a122f..703a7de78d1 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -702,7 +702,13 @@ struct brw_context
 
 #define BRW_PACKCOLOR8888(r,g,b,a)  ((r<<24) | (g<<16) | (b<<8) | a)
 
-
+struct brw_instruction_info {
+    char    *name;
+    int	    nsrc;
+    int	    ndst;
+    GLboolean is_arith;
+};
+extern const struct brw_instruction_info brw_opcodes[128];
 
 /*======================================================================
  * brw_vtbl.c
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 673a31c1dd6..41b8ecd6815 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -369,6 +369,7 @@ public:
       this->p = &c->func;
       this->brw = p->brw;
       this->intel = &brw->intel;
+      this->ctx = &intel->ctx;
       this->mem_ctx = talloc_new(NULL);
       this->shader = shader;
       this->fail = false;
@@ -431,6 +432,7 @@ public:
 
    struct brw_context *brw;
    struct intel_context *intel;
+   GLcontext *ctx;
    struct brw_wm_compile *c;
    struct brw_compile *p;
    struct brw_shader *shader;
@@ -1453,7 +1455,13 @@ fs_visitor::generate_code()
 	 generate_fb_write(inst);
 	 break;
       default:
-	 assert(!"not reached");
+	 if (inst->opcode < (int)ARRAY_SIZE(brw_opcodes)) {
+	    _mesa_problem(ctx, "Unsupported opcode `%s' in FS",
+			  brw_opcodes[inst->opcode].name);
+	 } else {
+	    _mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode);
+	 }
+	 this->fail = true;
       }
 
       if (annotation_len < p->nr_insn) {
diff --git a/src/mesa/drivers/dri/i965/brw_optimize.c b/src/mesa/drivers/dri/i965/brw_optimize.c
index afcd1fc15ac..cbed2bd5cb1 100644
--- a/src/mesa/drivers/dri/i965/brw_optimize.c
+++ b/src/mesa/drivers/dri/i965/brw_optimize.c
@@ -32,12 +32,7 @@
 #include "brw_defines.h"
 #include "brw_eu.h"
 
-static const struct {
-    char    *name;
-    int	    nsrc;
-    int	    ndst;
-    GLboolean is_arith;
-} inst_opcode[128] = {
+const struct brw_instruction_info brw_opcodes[128] = {
     [BRW_OPCODE_MOV] = { .name = "mov", .nsrc = 1, .ndst = 1, .is_arith = 1 },
     [BRW_OPCODE_FRC] = { .name = "frc", .nsrc = 1, .ndst = 1, .is_arith = 1 },
     [BRW_OPCODE_RNDU] = { .name = "rndu", .nsrc = 1, .ndst = 1, .is_arith = 1 },
@@ -94,7 +89,7 @@ static const struct {
 static INLINE
 GLboolean brw_is_arithmetic_inst(const struct brw_instruction *inst)
 {
-   return inst_opcode[inst->header.opcode].is_arith;
+   return brw_opcodes[inst->header.opcode].is_arith;
 }
 
 static const GLuint inst_stride[7] = {
@@ -122,7 +117,7 @@ brw_is_grf_written(const struct brw_instruction *inst,
                    int reg_index, int size,
                    int gen)
 {
-   if (inst_opcode[inst->header.opcode].ndst == 0)
+   if (brw_opcodes[inst->header.opcode].ndst == 0)
       return GL_FALSE;
 
    if (inst->bits1.da1.dest_address_mode != BRW_ADDRESS_DIRECT)
@@ -165,7 +160,7 @@ static GLboolean
 brw_is_mrf_written_alu(const struct brw_instruction *inst,
 		       int reg_index, int size)
 {
-   if (inst_opcode[inst->header.opcode].ndst == 0)
+   if (brw_opcodes[inst->header.opcode].ndst == 0)
       return GL_FALSE;
 
    if (inst->bits1.da1.dest_reg_file != BRW_MESSAGE_REGISTER_FILE)
@@ -298,7 +293,7 @@ static INLINE GLboolean
 brw_is_grf_read(const struct brw_instruction *inst, int reg_index, int size)
 {
    int i, j;
-   if (inst_opcode[inst->header.opcode].nsrc == 0)
+   if (brw_opcodes[inst->header.opcode].nsrc == 0)
       return GL_FALSE;
 
    /* Look at first source. We must take into account register regions to
@@ -306,7 +301,7 @@ brw_is_grf_read(const struct brw_instruction *inst, int reg_index, int size)
     * since we do not take into account the fact that some complete registers
     * may be skipped
     */
-   if (inst_opcode[inst->header.opcode].nsrc >= 1) {
+   if (brw_opcodes[inst->header.opcode].nsrc >= 1) {
 
       if (inst->bits2.da1.src0_address_mode != BRW_ADDRESS_DIRECT)
          if (inst->bits1.ia1.src0_reg_file == BRW_GENERAL_REGISTER_FILE)
@@ -341,7 +336,7 @@ brw_is_grf_read(const struct brw_instruction *inst, int reg_index, int size)
    }
 
    /* Second src register */
-   if (inst_opcode[inst->header.opcode].nsrc >= 2) {
+   if (brw_opcodes[inst->header.opcode].nsrc >= 2) {
 
       if (inst->bits3.da1.src1_address_mode != BRW_ADDRESS_DIRECT)
          if (inst->bits1.ia1.src1_reg_file == BRW_GENERAL_REGISTER_FILE)