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authorMarek Olšák <[email protected]>2017-07-30 16:41:39 +0200
committerMarek Olšák <[email protected]>2017-08-01 17:06:38 +0200
commit94965b8219508954a5fddd74e7c6de4503cd9931 (patch)
tree27dfc0c245f0d583f54c83005fafc48344d5ede1
parentb9fc9d3f241758ed8a274be7abf68bf448653508 (diff)
radeonsi: set up HTILE in descriptors only when level 0 is accessible
Compression isn't enabled with non-zero levels. Reviewed-by: Nicolai Hähnle <[email protected]>
-rw-r--r--src/gallium/drivers/radeonsi/si_descriptors.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 18b070ba3a2..b080562348c 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -432,7 +432,7 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
if (sscreen->b.chip_class <= VI)
meta_va += base_level_info->dcc_offset;
- } else if (tex->tc_compatible_htile) {
+ } else if (tex->tc_compatible_htile && first_level == 0) {
meta_va = tex->resource.gpu_address + tex->htile_offset;
}