diff options
| author | Samuel Pitoiset <[email protected]> | 2019-07-18 10:14:09 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2019-07-18 10:37:10 +0200 |
| commit | 6e5e4bf0505f0723e500f2827d45c5d0191fb098 (patch) | |
| tree | 20785a02ffadab7d09f21ce4617fe681f6d9c84d | |
| parent | 8c692ff5125b322bbfff84c93f7798b1b94a379e (diff) | |
radv/gfx10: set BREAK_WAVE_AT_EOI if TES or GS enable the primitive ID
Signed-off-by: Samuel Pitoiset <[email protected]>
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index b11d79f4811..a7ff0e2d139 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -3445,6 +3445,14 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs, bool break_wave_at_eoi = false; unsigned nparams; + if (es_type == MESA_SHADER_TESS_EVAL) { + struct radv_shader_variant *gs = + pipeline->shaders[MESA_SHADER_GEOMETRY]; + + if (es_enable_prim_id || (gs && gs->info.info.uses_prim_id)) + break_wave_at_eoi = true; + } + nparams = MAX2(outinfo->param_exports, 1); radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, S_0286C4_VS_EXPORT_COUNT(nparams - 1) | |