diff options
| author | Anuj Phogat <[email protected]> | 2017-10-31 09:28:09 -0700 |
|---|---|---|
| committer | Anuj Phogat <[email protected]> | 2017-11-03 14:30:34 -0700 |
| commit | 6c681b4cc1aab20f280dfce88d77896b64588144 (patch) | |
| tree | 54b239254366220d4cbaf9481e0d67727ecd7e8f | |
| parent | d3d0fe4572f62474b86ef3a68405046c68b54062 (diff) | |
i965/gen10: Enable float blend optimization
This optimization is enabled for previous generations too.
See Mesa commit c17e214a6b
On CNL this bit has been moved to CACHE_MODE_SS register.
Signed-off-by: Anuj Phogat <[email protected]>
Reviewed-by: Nanley Chery <[email protected]>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 3 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_state_upload.c | 6 |
2 files changed, 9 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 270cdf29db3..105fff3548f 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1688,6 +1688,9 @@ enum brw_pixel_shader_coverage_mask_mode { # define GEN8_L3CNTLREG_ALL_ALLOC_SHIFT 25 # define GEN8_L3CNTLREG_ALL_ALLOC_MASK INTEL_MASK(31, 25) +#define GEN10_CACHE_MODE_SS 0x0e420 +#define GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4) + #define INSTPM 0x20c0 # define INSTPM_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE (1 << 6) diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index 9e1cf54abda..9e64213c2e7 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -62,6 +62,12 @@ brw_upload_initial_gpu_state(struct brw_context *brw) brw_upload_invariant_state(brw); + if (devinfo->gen == 10) { + brw_load_register_imm32(brw, GEN10_CACHE_MODE_SS, + REG_MASK(GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE) | + GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE); + } + if (devinfo->gen == 9) { /* Recommended optimizations for Victim Cache eviction and floating * point blending. |