diff options
| author | Marek Olšák <[email protected]> | 2017-06-05 19:59:06 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2017-06-07 19:38:42 +0200 |
| commit | 66176e6f14269937f64225d94779e0592eed6a1e (patch) | |
| tree | e8bac5103c7e9c6504de92b49bc95fe41b95e8cc | |
| parent | d2ee423b69660a219c031abad101decd0ecae327 (diff) | |
radeonsi: don't use 1D tiling for Z/S on VI to get TC-compatible HTILE
It's always good to have fewer decompress blits.
Reviewed-by: Nicolai Hähnle <[email protected]>
| -rw-r--r-- | src/gallium/drivers/radeon/r600_texture.c | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c index 4d72b86f4e4..046fb906a2f 100644 --- a/src/gallium/drivers/radeon/r600_texture.c +++ b/src/gallium/drivers/radeon/r600_texture.c @@ -1281,6 +1281,8 @@ r600_choose_tiling(struct r600_common_screen *rscreen, { const struct util_format_description *desc = util_format_description(templ->format); bool force_tiling = templ->flags & R600_RESOURCE_FLAG_FORCE_TILING; + bool is_depth_stencil = util_format_is_depth_or_stencil(templ->format) && + !(templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH); /* MSAA resources must be 2D tiled. */ if (templ->nr_samples > 1) @@ -1290,6 +1292,14 @@ r600_choose_tiling(struct r600_common_screen *rscreen, if (templ->flags & R600_RESOURCE_FLAG_TRANSFER) return RADEON_SURF_MODE_LINEAR_ALIGNED; + /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on VI, + * which requires 2D tiling. + */ + if (rscreen->chip_class == VI && + is_depth_stencil && + (templ->flags & PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY)) + return RADEON_SURF_MODE_2D; + /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */ if (rscreen->chip_class >= R600 && rscreen->chip_class <= CAYMAN && (templ->bind & PIPE_BIND_COMPUTE_RESOURCE) && @@ -1300,9 +1310,9 @@ r600_choose_tiling(struct r600_common_screen *rscreen, /* Handle common candidates for the linear mode. * Compressed textures and DB surfaces must always be tiled. */ - if (!force_tiling && !util_format_is_compressed(templ->format) && - (!util_format_is_depth_or_stencil(templ->format) || - templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH)) { + if (!force_tiling && + !is_depth_stencil && + !util_format_is_compressed(templ->format)) { if (rscreen->debug_flags & DBG_NO_TILING) return RADEON_SURF_MODE_LINEAR_ALIGNED; |