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authorRob Clark <[email protected]>2017-11-05 09:15:08 -0500
committerRob Clark <[email protected]>2017-11-12 12:28:59 -0500
commit62981bbe656db1de5311ac5c23a69122748e681b (patch)
tree6685e231f225714521af41929acff9eb5ed3a71d
parentbedbe7f90c811dcf47975008efbd1b54dbdf2756 (diff)
freedreno/ir3: turn on std430 packing
Seems to fix dEQP compute related tests.. and matches what i965 does, so perhaps there is some assumption that std430 packing is on by default somewhere in NIR?
-rw-r--r--src/gallium/drivers/freedreno/freedreno_screen.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c
index 7910bbbdcd5..6a44d7543d1 100644
--- a/src/gallium/drivers/freedreno/freedreno_screen.c
+++ b/src/gallium/drivers/freedreno/freedreno_screen.c
@@ -324,13 +324,18 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
case PIPE_CAP_QUERY_SO_OVERFLOW:
case PIPE_CAP_MEMOBJ:
- case PIPE_CAP_LOAD_CONSTBUF:
case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
case PIPE_CAP_TILE_RASTER_ORDER:
case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
return 0;
+ case PIPE_CAP_LOAD_CONSTBUF:
+ /* name is confusing, but this turns on std430 packing */
+ if (is_ir3(screen))
+ return 1;
+ return 0;
+
case PIPE_CAP_MAX_VIEWPORTS:
return 1;