diff options
| author | Samuel Pitoiset <[email protected]> | 2017-11-30 14:32:57 +0100 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2017-11-30 21:37:58 +0100 |
| commit | 4eab78b03cc3695d78e21fdb3d760975e0ae1fda (patch) | |
| tree | 93cf357ccc0c05f2fde82f066c6293b4caf74758 | |
| parent | 7776dc32eb10c8cf4ec9720e1c8a3bd8fd3a7d1d (diff) | |
radv: do not store gfx9_epitch in radv_color_buffer_info
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 7 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_device.c | 3 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_private.h | 1 |
3 files changed, 4 insertions, 7 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index bd72ba2a878..18a1c55ad18 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1181,9 +1181,10 @@ radv_emit_depth_biais(struct radv_cmd_buffer *cmd_buffer) static void radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer, int index, - struct radv_color_buffer_info *cb) + struct radv_attachment_info *att) { bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI; + struct radv_color_buffer_info *cb = &att->cb; if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) { radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11); @@ -1204,7 +1205,7 @@ radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer, radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32); radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4, - cb->gfx9_epitch); + S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch)); } else { radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11); radeon_emit(cmd_buffer->cs, cb->cb_color_base); @@ -1464,7 +1465,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer) radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8); assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT); - radv_emit_fb_color_state(cmd_buffer, i, &att->cb); + radv_emit_fb_color_state(cmd_buffer, i, att); radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i); } diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 8e5ae0bc46e..336cb125a09 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -3077,9 +3077,6 @@ radv_initialise_color_surface(struct radv_device *device, cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) | S_028C68_MIP0_HEIGHT(iview->extent.height - 1) | S_028C68_MAX_MIP(iview->image->info.levels - 1); - - cb->gfx9_epitch = S_0287A0_EPITCH(iview->image->surface.u.gfx9.surf.epitch); - } } diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index addd35e5ce1..e8c7af7c641 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -1456,7 +1456,6 @@ struct radv_color_buffer_info { uint32_t cb_clear_value0; uint32_t cb_clear_value1; uint32_t micro_tile_mode; - uint32_t gfx9_epitch; }; struct radv_ds_buffer_info { |