diff options
| author | Kenneth Graunke <[email protected]> | 2019-05-03 16:39:18 -0700 |
|---|---|---|
| committer | Francisco Jerez <[email protected]> | 2019-10-11 12:24:16 -0700 |
| commit | 44754279ace72bc36b016f9ca519141ea4cad038 (patch) | |
| tree | 5b6410d707f11dfdaf96c15b970a5c8e4b6fea35 | |
| parent | c92fb60007f9c73a4c174f5f4cbce57fbc5118f4 (diff) | |
intel/fs/gen12: Use TCS 8_PATCH mode.
Reviewed-by: Francisco Jerez <[email protected]>
| -rw-r--r-- | src/intel/compiler/brw_compiler.c | 3 | ||||
| -rw-r--r-- | src/intel/compiler/brw_vec4_tcs.cpp | 11 |
2 files changed, 8 insertions, 6 deletions
diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c index 6404339f06f..06b70193dd6 100644 --- a/src/intel/compiler/brw_compiler.c +++ b/src/intel/compiler/brw_compiler.c @@ -101,7 +101,8 @@ brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo) compiler->precise_trig = env_var_as_boolean("INTEL_PRECISE_TRIG", false); compiler->use_tcs_8_patch = - devinfo->gen >= 9 && (INTEL_DEBUG & DEBUG_TCS_EIGHT_PATCH); + devinfo->gen >= 12 || + (devinfo->gen >= 9 && (INTEL_DEBUG & DEBUG_TCS_EIGHT_PATCH)); if (devinfo->gen >= 10) { /* We don't support vec4 mode on Cannonlake. */ diff --git a/src/intel/compiler/brw_vec4_tcs.cpp b/src/intel/compiler/brw_vec4_tcs.cpp index 9d6c4f326a4..3ce5e268e27 100644 --- a/src/intel/compiler/brw_vec4_tcs.cpp +++ b/src/intel/compiler/brw_vec4_tcs.cpp @@ -360,12 +360,13 @@ brw_compile_tcs(const struct brw_compiler *compiler, nir->info.system_values_read & (1 << SYSTEM_VALUE_PRIMITIVE_ID); if (compiler->use_tcs_8_patch && - nir->info.tess.tcs_vertices_out <= 16 && + nir->info.tess.tcs_vertices_out <= (devinfo->gen >= 12 ? 32 : 16) && 2 + has_primitive_id + key->input_vertices <= 31) { - /* 3DSTATE_HS imposes two constraints on using 8_PATCH mode. First, - * the "Instance" field limits the number of output vertices to [1, 16]. - * Secondly, the "Dispatch GRF Start Register for URB Data" field is - * limited to [0, 31] - which imposes a limit on the input vertices. + /* 3DSTATE_HS imposes two constraints on using 8_PATCH mode. First, the + * "Instance" field limits the number of output vertices to [1, 16] on + * gen11 and below, or [1, 32] on gen12 and above. Secondly, the + * "Dispatch GRF Start Register for URB Data" field is limited to [0, + * 31] - which imposes a limit on the input vertices. */ vue_prog_data->dispatch_mode = DISPATCH_MODE_TCS_8_PATCH; prog_data->instances = nir->info.tess.tcs_vertices_out; |