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authorEric Anholt <[email protected]>2018-01-04 22:47:54 -0800
committerEric Anholt <[email protected]>2018-01-12 21:54:18 -0800
commit2bd378647bebd41338baf9c6a9297a3a72c84e84 (patch)
tree2c9794131a43ce27dd091215d649f4586d29a376
parent5f227ac2104e08ad434c78a472ef9ac21ebdfe73 (diff)
broadcom/vc5: Add support for QPU pack/unpack/disasm of small immediates.
-rw-r--r--src/broadcom/qpu/qpu_disasm.c16
-rw-r--r--src/broadcom/qpu/qpu_instr.h10
-rw-r--r--src/broadcom/qpu/qpu_pack.c63
-rw-r--r--src/broadcom/qpu/tests/qpu_disasm.c6
4 files changed, 94 insertions, 1 deletions
diff --git a/src/broadcom/qpu/qpu_disasm.c b/src/broadcom/qpu/qpu_disasm.c
index 73b43f8c3d6..32e7ba12a4c 100644
--- a/src/broadcom/qpu/qpu_disasm.c
+++ b/src/broadcom/qpu/qpu_disasm.c
@@ -62,7 +62,21 @@ v3d_qpu_disasm_raddr(struct disasm_state *disasm,
if (mux == V3D_QPU_MUX_A) {
append(disasm, "rf%d", instr->raddr_a);
} else if (mux == V3D_QPU_MUX_B) {
- append(disasm, "rf%d", instr->raddr_b);
+ if (instr->sig.small_imm) {
+ uint32_t val;
+ MAYBE_UNUSED bool ok =
+ v3d_qpu_small_imm_unpack(disasm->devinfo,
+ instr->raddr_b,
+ &val);
+
+ if ((int)val >= -16 && (int)val <= 15)
+ append(disasm, "%d", val);
+ else
+ append(disasm, "0x%08x", val);
+ assert(ok);
+ } else {
+ append(disasm, "rf%d", instr->raddr_b);
+ }
} else {
append(disasm, "r%d", mux);
}
diff --git a/src/broadcom/qpu/qpu_instr.h b/src/broadcom/qpu/qpu_instr.h
index cab1885acc4..468fe89facd 100644
--- a/src/broadcom/qpu/qpu_instr.h
+++ b/src/broadcom/qpu/qpu_instr.h
@@ -395,6 +395,16 @@ v3d_qpu_flags_unpack(const struct v3d_device_info *devinfo,
struct v3d_qpu_flags *cond);
bool
+v3d_qpu_small_imm_pack(const struct v3d_device_info *devinfo,
+ uint32_t value,
+ uint32_t *packed_small_immediate);
+
+bool
+v3d_qpu_small_imm_unpack(const struct v3d_device_info *devinfo,
+ uint32_t packed_small_immediate,
+ uint32_t *small_immediate);
+
+bool
v3d_qpu_instr_pack(const struct v3d_device_info *devinfo,
const struct v3d_qpu_instr *instr,
uint64_t *packed_instr);
diff --git a/src/broadcom/qpu/qpu_pack.c b/src/broadcom/qpu/qpu_pack.c
index 68df6fe64c4..161e24f0300 100644
--- a/src/broadcom/qpu/qpu_pack.c
+++ b/src/broadcom/qpu/qpu_pack.c
@@ -255,6 +255,69 @@ v3d_qpu_sig_pack(const struct v3d_device_info *devinfo,
return false;
}
+static inline unsigned
+fui( float f )
+{
+ union {float f; unsigned ui;} fi;
+ fi.f = f;
+ return fi.ui;
+}
+
+static const uint32_t small_immediates[] = {
+ 0, 1, 2, 3,
+ 4, 5, 6, 7,
+ 8, 9, 10, 11,
+ 12, 13, 14, 15,
+ -16, -15, -14, -13,
+ -12, -11, -10, -9,
+ -8, -7, -6, -5,
+ -4, -3, -2, -1,
+ 0x3b800000, /* 2.0^-8 */
+ 0x3c000000, /* 2.0^-7 */
+ 0x3c800000, /* 2.0^-6 */
+ 0x3d000000, /* 2.0^-5 */
+ 0x3d800000, /* 2.0^-4 */
+ 0x3e000000, /* 2.0^-3 */
+ 0x3e800000, /* 2.0^-2 */
+ 0x3f000000, /* 2.0^-1 */
+ 0x3f800000, /* 2.0^0 */
+ 0x40000000, /* 2.0^1 */
+ 0x40800000, /* 2.0^2 */
+ 0x41000000, /* 2.0^3 */
+ 0x41800000, /* 2.0^4 */
+ 0x42000000, /* 2.0^5 */
+ 0x42800000, /* 2.0^6 */
+ 0x43000000, /* 2.0^7 */
+};
+
+bool
+v3d_qpu_small_imm_unpack(const struct v3d_device_info *devinfo,
+ uint32_t packed_small_immediate,
+ uint32_t *small_immediate)
+{
+ if (packed_small_immediate >= ARRAY_SIZE(small_immediates))
+ return false;
+
+ *small_immediate = small_immediates[packed_small_immediate];
+ return true;
+}
+
+bool
+v3d_qpu_small_imm_pack(const struct v3d_device_info *devinfo,
+ uint32_t value,
+ uint32_t *packed_small_immediate)
+{
+ STATIC_ASSERT(ARRAY_SIZE(small_immediates) == 48);
+
+ for (int i = 0; i < ARRAY_SIZE(small_immediates); i++) {
+ if (small_immediates[i] == value) {
+ *packed_small_immediate = i;
+ return true;
+ }
+ }
+
+ return false;
+}
bool
v3d_qpu_flags_unpack(const struct v3d_device_info *devinfo,
diff --git a/src/broadcom/qpu/tests/qpu_disasm.c b/src/broadcom/qpu/tests/qpu_disasm.c
index 4f6ded73d48..27dc184f76e 100644
--- a/src/broadcom/qpu/tests/qpu_disasm.c
+++ b/src/broadcom/qpu/tests/qpu_disasm.c
@@ -46,6 +46,12 @@ static const struct {
{ 33, 0x1c0a0dfde2294000ull, "fcmp.ifna rf61.h, r4.abs, r2.l; vfmul rf55, r2.hh, r1" },
{ 33, 0x2011c89b402cc000ull, "fsub.norz rf27, r4.abs, r1.abs; vfmul.ifa rf34, r3.swp, r1" },
+ /* small immediates */
+ { 33, 0x5de24398bbdc6218ull, "vflb.andnn rf24 ; fmul rf14, -8, rf8.h" },
+ { 33, 0x25ef83d8b166f00full, "vfmin.pushn rf24, 15.ff, r5; smul24.ifnb rf15, r1, r3" },
+ { 33, 0xadedcdf70839f990ull, "faddnf.pushc rf55, -16.l, r3.abs; fmul.ifb rf55.l, rf38.l, r1.h" },
+ { 33, 0x7dff89fa6a01f020ull, "fsub.nornc rf58.h, 0x3b800000.l, r3.l; fmul.ifnb rf39, r0.h, r0.h" },
+
/* branch conditions */
{ 33, 0x02000006002034c0ull, "b.anyap rf19" },
{ 33, 0x02679356b4201000ull, "b.anyap -1268280496" },